2.4GHz 互補式金氧半導體正交相位壓控震盪器及除頻器及其在非整數除頻頻率合成器中的應用

Abstract

本篇論文描述一個工作在2.4GHz 互補式金氧半導體正交相位壓控震盪器及除頻器，並將這兩個電路應用在非整數除頻頻率合成器中。 在本論文中提出了一個採用全新架構的正交相位壓控震盪器，以台灣積體電路製造股份有限公司以0.25微米製程實現，並自行量測完成。量測結果顯示本架構產生的正交相位訊號可使大部分低鏡像信號架構達到足夠的鏡像頻率拒斥。本論文也提出一個工作電壓1.5伏特雙模除頻器，其中使用四相位注入鎖定除頻器並利用相位切換技巧有效減低功率消耗，工作在2.4~2.5GHz頻帶約消耗7mW功率。 本論文並以delta-sigma非整數除頻頻率合成器來驗證上述兩電路的功能。此頻率合成器包括相位頻率偵測器、傳統電流幫浦、三階濾波器、本文提出的四相位壓控震盪器及雙模除頻器。

A design of 2.4GHz CMOS quadrature VCO and frequency divider and their applications in fractional-N frequency synthesizer is described in this thesis. The proposed whole new quadrature generator is fabricated using a standard TSMC 0.25um CMOS process and has been measured completely. The measurement results of this chip meet the requirement that provides sufficient image rejection ratio in the most RF receiver architecture. A 1.5v 32/33 dual-modulus frequency divider is also presented in this thesis. It combines quadrature injection-locked frequency divider and phase switching technique to reduce power consumption. It works at frequency band 2.4~2.5GHz and consumes about 7mW. A delta-sigma fractional-N frequency synthesizer including two blocks mentioned above is presented. This frequency synthesizer combines these two blocks and proves their functionality. This synthesizer introduces conventional deadzone-less PFD, conventional charge-pump, third order loop filter, proposed quadrature VCO, proposed quadrature injection-locked divider combining with phase switching technique and an all digital third order single bit delta-sigma modulator with mash3 delta-sigma modulator dithering input as fractional modulus generator.