SONOS元件內儲存電子之能量分佈與傳輸行為

Abstract

本篇論文主要著重於SONOS元件內儲存電子之能量分布以及電子傳輸行為所引發可靠性議題之討論。這些可靠性議題主要包括：寫入狀態臨界電壓之漂移效應（program state threshold voltage shift）、第二位元效應（second bit effect）、以及難以抹除效應（hard to erase effect）。而在此研究中，SONOS元件為一n型通道金氧半場效電晶體加一ONO閘極而構成。 根據我們過去的研究指出，寫入狀態之資料流失主要是來自於儲存於氮化矽中之電子藉著Frenkel-Poole激發並經由氧化層缺陷之輔助而導致穿隧，進而造成資料流失。因此藉由加速驅使電子自缺陷中脫離並量測其電流大小，將使我們得以一窺氮化矽層中儲存電荷之能量分布情形。此外，為了觀察在寫入狀態下電子水平傳輸所引發之暫態效應，吾人亦建立了一套微秒暫態量測電路（micro-second transient measurement circuit）。藉著此電路的輔助，我們將得以觀測在二位元操作模式下因位元線干擾所引發的可靠性議題，其中又以影響最為顯著的難以抹除效應為最。隨著寫入/抹除的次數增加，此種位元線干擾所引發的儲存電荷橫向擴散現象將越趨嚴重，幸運的是，藉著使用吾人在本篇論文中所提及之寫入波形，此種負面現象將得以舒緩。

This thesis will focus on the discussion of trapped charge energy distribution in nitride layer and reliability issues induced by trapped charge lateral transport in a SONOS type trapping storage cell, which include program state threshold voltage shift, second bit effect, and hard to erase effect. In this study, the SONOS cell is made of a n-channel MOSFET with an oxide-nitride-oxide gate structure. Since the program state data retention loss was found to be attributed mostly to nitride charge escape by Frenkel-Poole emission and oxide trap assisted tunneling in our previous studies, the nitride charge detrapping current will be used to profile the energy distribution of trapped charge in SiN layer. In addition, a micro-second transient measurement circuit is set up to investigate the transient effect of trapped charge lateral transport. Therefore, the reliability issues, especially the significant erase degradation effect, induced by bit-line disturb in two-bit operation are observed. As P/E cycle number increases, trapped charge lateral transport induced by bit-line disturb will be enhanced. A new program pattern can be used to reduce these effects.