考慮晶片上互感及電阻、電感、電容雜訊之漏話導向電路佈局

Abstract

當深次微米技術演進至0.18 微米之下，雜訊效應成為電路設計者所無法忽視的一個重要問題。本論文提供一新穎的漏話導向之電路佈局演算法，用於消減晶片上因互感及電阻、電感、電容所產生之雜訊。我們將證明在佈局時僅考慮因電阻與電容所引起之雜訊，將過分樂觀化實際電路所產生之雜訊效應。實驗結果說明， 我們提供之演算法相較於面積導向之佈局法，僅平均多增加8.4%的面積，但卻減低了44.1%的機率雜訊值、並縮短了30.1%的總估計線長。而相較於壅塞導向與電阻、電容雜訊導向之佈局法，我們也分別平均改善了15.9%、8.9%的機率雜訊值，以及縮短14.9%與6.8%的總估計線長。

As the deep-submicron technologies scale down to 0.18 µm, the crosstalk noise has become a critical issue which designer cannot neglect. In the thesis, a novel crosstalk-driven placement algorithm for on-chip mutual inductance and RLC noise consideration will be proposed. We also demonstrate that only take account of the RC noise during placement will be excessively optimistic in the noise effects produced by designed circuits. Results show that our approach can reduce 44.1% probabilistic RLC noise and improve 30.1% total estimated wirelength on average than the area-driven placement only at the cost of 8.4% increase of total area. For the congestion-driven and RC-driven placement, our algorithm also achieves 15.9% and 8.9% improvement on average in probabilistic RLC noise, and averagely minimizes 14.9% as well as 6.8% total estimated wirelength, respectively.