CMOS元件1/f雜訊特性分析與模擬

Abstract

本文中探討了高效能類比0.13mm CMOS元件裡的口袋埋置效應。我們的研究成果顯示了口袋埋置製程會造成雜訊特性的劣化﹐因其造成通道方向上的不均勻門檻電壓。我們提出了一個可分析的模型來計算口袋埋置效應﹐並將載子濃度分佈的模擬與實驗結果相比較。 本文中另外探討了基底效應在低頻雜訊上所造成的影響。打了口袋埋置的元件相較於沒有打口袋埋置元件來說﹐它表現出較差的低頻雜訊特性。我們從模擬中了解了載子濃度分佈在這兩種不同元件中的差異性﹐而模擬的結果和實驗結論相吻合。 由通道熱載子寫入所造成的不均勻門檻電壓會增加源極電流雜訊﹐可是FN寫入則否。這說明了載子變動在低頻雜訊的重要性。而藉由我們對低頻雜訊的了解﹐藉由低頻雜訊實驗來淬取出元件所儲存的電荷分佈是可行的。基於不均勻門檻電壓所推導出的兩區域模型將被用來處理這件工作。

Pocket implant effect on drain current flicker noise in 0.13mm CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will degrade device noise characteristics primarily due to enhanced non-uniform threshold voltage distribution along the channel. An analytical flicker noise model to take into account a pocket doping effect is proposed. And simulation of drain current flicker noise including channel carrier distribution is presented and is compared to the experiment results. Body effect on low frequency is studied in this thesis. The pocket implant device shows worse behavior in low frequency noise. The difference of carrier distribution between pocket implant device and non-pocket device is clarified by simulation. Non-uniform threshold voltage distribution along the channel resulting from channel hot electron stress would increase drain current flicker noise. And uniform FN stress wouldn’t cause the degradation of low frequency noise. That implies the impact of charge number fluctuation in flicker noise. According to the unified flicker noise model, it’s possible to extract trapped charge profile without using 2D device simulation. A two-region model based on non-uniform threshold voltage distribution is used to extract the trapped charge lateral profile.