積體電路射頻串音干擾抑制

Abstract

本篇論文的主旨乃是有鑑於在未來的單晶片系統（SoC）時代與奈米（Nano）紀元中，製程尺寸愈來愈小、工作頻率愈來愈快，及操作電壓愈來愈低時致使積體電路系統中引起的射頻串音干擾，將會愈來愈嚴重地影響電路及整個系統的特性與表現，甚至損毀電路元件。故我們提出一種完全嶄新的佈局方法來加以抑制此不必要的雜訊干擾，以幫助整體電路系統能正常運作。而我們所提出的方法乃是奠基於非遮蔽雙絞線對於雜訊抑制的觀念，加以引伸至應用到積體電路的層次以獲得對於雜訊干擾抑制的效果。 本篇論文是以非遮蔽雙絞線的原理為立論，輔以HFSS對設計結構在1GHz到3GHz間進行模擬，並以TSMC 0.35μm CMOS製程加以實現，最後為了盡量避免非必要的干擾性因素，我們是採用網路分析儀做晶片上（on-wafer）的直接量測，而與模擬結果做比較與呼應。 而我們在論文中共設計九種金屬連接線（interconnection）的結構，以做為相互的評比與對照，其中這九種結構其都被設計為1300μm的長度，以突顯串音干擾的效應，而整個晶片面積大小為1750μm × 1750μm。

The goal of our thesis is in consideration of the predictably severer interference to the characteristics and performances of circuits or systems even the components in VLSI chips from the RF crosstalk effects due to smaller process dimensions, quicker working frequency and lower operating voltage in future, especially in the SoC age and the Nano era. In our thesis, consequently, we will ahead propose a completely new approach based on the concepts of unshielded twisted pair (UTP) to reduce the unwanted noise interference occurring in VLSI level and protect the whole circuit system from failure. Our thesis is built up on the basis of UTP with the simulation under the frequency range from 1GHz to 3GHz by HFSS, and we furthermore implement our designed structures on chip through the TSMC 0.35μm logic silicide process. Eventually, for the sake of comparison with the simulation results, we adopt the on-wafer measurement by the network analyzer to eliminate the unexpected interfering factors. In our thesis, nine different interconnection structures are presented for the purpose of contrast. Additionally, all of the interconnections are designed to be 1300μm in length to emphasize the effects of crosstalk interference. Moreover, the size of whole chip is 1750μm × 1750μm.