具複雜度感知的係數量化及有限脈衝響應之濾波器設計

Abstract

在數位信號處理的應用中有限脈衝響應濾波器被廣泛的使用，而其中經常需要為了面積和功率最佳化的需求而作客戶化的實現。這篇論文提出一個新穎的係數量化演算法，對有限脈衝響應的係數作最佳化。我們提出的演算法在量化係數間去精確的分配一個預先定義好的加法量預算並對濾波器的性能作最大化。Signed digit表示法以及我們提出改善的common subexpression elimination方法都被應用在於位元位準上對複雜度的最小化。因此，設計者可以明確地在實現複雜度與量化誤差之間作取捨。在架構層次上面，我們提出一個有效的演算法來避免溢位以及對中間變數的最小化。這可以縮小加法器大小或者改善捨位誤差。我們也提出一個藉由retiming來進一步減少silicon area的系統化合成位元序列架構的方法。在我們的實驗上，我們的optimal signed digit encoding及其改善的common subexpression elimination方法對於相同的量化誤差能減少50.8%~51.2%的加法個數。此外，位元序列化對於速度需求較低的應用可以更進一步節省 32.99%~34.97%的面積(以gate count作估算)。另外，我們在論文最後提出一個可程式化的有限脈衝響應濾波器架構來證明我們能夠有效的在量化誤差上與執行時間上作取捨。

FIR filters are widely used in DSP applications, where customized implementations are frequently desirable for area or power optimization. This thesis presents a novel quantization algorithm to optimize the FIR coefficients for efficient implementations. The proposed algorithm precisely distributes a pre-defined addition budget among the quantized coefficients to maximize the filter performance. Both signed-digit representations and our improved common subexpression elimination (CSE) are applied to minimize the complexity at the bit level. Thus, the designers can explicitly trade the implementation complexity for the quantization noise. At the architecture level, we propose an effective algorithm to prevent overflow and to minimize the wordlength of the intermediate variables, which either reduce the adder sizes or improve the round-off error. We describe the systematic synthesis of bit-serial architectures by retiming to further reduce the silicon area. In our experiments, our improved CSE with the optimal signed-digit coding can reduce 50.8%~51.2% additions for comparable quantization errors. Moreover, the bit-serialization can further save 32.99%~34.97% area (estimated in gate counts) for less timing-critical applications. By the way, we also propose a programmable FIR architecture to demonstrate the effectiveness of the trade-offs between quantization errors and execution time at the end of this thesis.