802.11a 基頻發送端及同步電路設計

Abstract

本論文提出一個低延遲、簡單控制的IEEE 802.11a基頻發送端與一個低殘餘載波頻率漂移的802.11a同步電路。所提出的基頻發送端的架構中，共包含有九個主要的模組。利用控制模組驅動信號的開關，所提出的基頻發送端可輕易地擁有多種資料傳輸速率的能力。同步的工作包含了時間與載波頻率的同步、等化器及殘餘相位的追蹤。本論文提出了時間與載波頻率的同步電路。硬體行為模擬是藉由安捷倫ADS平台與The MathWorks的MATLAB平台。此外，透過FPGA的實現來達成硬體的設計驗證。根據802.11a標準的規範，整個基頻發送端與同步的電路的設計都使用20 MHz的時脈頻率來當作系統的工作頻率。最後，所提出的基頻發送端與同步電路的FPGA等效gate count分別為146176與156063。

In this thesis, an easy controlled and low-latency IEEE WLAN 802.11a transmitter and synchronization with low remaining CFO are presented. For the transmitter (packet composer), it contains nine main modules with each having a chip-enable signal to achieve the design goals as easy controlled. For the synchronization, burst timing estimation, carrier frequency offset (CFO) estimation, equalizer and additional phase correction are established. And a hardware design for timing estimation and CFO estimation is provided. Behavior simulation is done by ADS co-simulation and Matlab. FPGA verification and measurement has been done. For 802.11a transmitter, it can have desired result under 20 MHz clock rates that defined by 802.11a standard and so can the synchronization hardware. The equivalent gate counts under FPGA implementation are 146176 and 156063 for transmitter and timing synchronization.