針對電晶體電路之階層模組粹取

Abstract

隨著現今積體電路設計的複雜度越來越高，在設計流程中每一個層次之間的設計驗證成為一個十分重要且充滿挑戰的課題。在本篇論文中，我們提出一個相當有效率的方式，從低階層次中重建出完整電路階層。我們利用電路結構相等特性的擴展方式，找尋在每一個電路設計層次中存在的相同重複模組，以達到電路階層重建的目標。我們的方式在只需最原始的低階電晶體層次(flatten netlist)情形下，不需要其他任何額外的電路資訊，並且在時間與空間的利用上都十分的節省。在我們對於許多包含組合、循序與記憶體電路的實驗結果顯示，我們的方法不但能重建出絕大部分的電路階層，同時對電路描述的化簡，也有相當顯著的成效。

The growing of modern IC design complexity leads the consistency check and design verification during every level in design flow to be an important and challenged issue. In this thesis, we propose an efficient approach to rebuild the hierarchical level from low level circuits. Our approach is based on the structure equivalent expansion algorithm to find repeated submodules in every circuit level to reconstruct circuit hierarchy. Without any addition library information, our approach is quite efficient in both time and space complexities by using only flatten netlists. The experiments on many real circuits containing combinational, sequential, and memory circuits show that our approach can rebuild most circuit hierarchical levels and also reduce the verification effort of the circuits.