5.8GHz CMOS低雜訊放大器的設計及新穎的雜訊模型之研究

Abstract

由於現今矽電晶體的高度發展，其閘極長度亦隨之縮小，使得其元件在微波電路的設計上，漸漸受到RF工程師的關注與討論。為了要確保電路在高頻時仍有我們所需的特性並且縮短設計的週期，精確的元件模型的建立是必要且不可缺乏的。本論文實現矽高頻電晶體的高頻模型並針對高頻的最小雜訊指數與閘極數目之間的關係提出一初步的說明:高頻的最小雜訊指數是與電晶體本身的雜訊及電晶體主動區外部閘極至基底的損耗的交互效應有關。並用一新穎的雜訊模型模擬之。由以上的研究，找出了最低雜訊指數的電晶體大小，並將它實現在低雜訊放大器的輸入電晶體。再者，我們分析了源極電感回授之架構，並分別說明它對 和 以及對增益圓和雜訊圓的影響。最後，實現了一5.8GHz採用源極電感回授的低雜訊放大器來印證我們的論點。

Recent advances in Si MOSFET’s with a submicrometer gate length have made these devices an attractive candidate for RF designers to implement in microwave circuits. In order to ensure the circuit performance for the required frequency bands and also shorten the design cycle, device models are very critical. This thesis accomplishes the high frequency model of RF Si MOSFET and interprets the relationship between and gate finger number at high frequency: the total at high frequency is related to the combined effect of the MOSFET and gate to substrate loss outside the active region. And a novel noise model of MOSFET is developed and simulated to confirm our opinion. From above, the MOSFET size with minimum noise figure is presented and used later as the input stage of the LNA. Furthermore, the architecture of source degeneration is analyzed in terms of and as well as gain circle and noise circle. Finally, a 5.8GHz CMOS low noise amplifier with source degeneration is designed and measured to confirm our investigation.