标题: | 具比例式记忆或大邻近层之细胞非线性网路设计与分析及其应用 Design and Analysis of Cellular Nonlinear Networks with Ratio Memory or Large-Neighborhood and their Applications |
作者: | 郑秋宏 Chiu-Hung Cheng 吴重雨 Chung-Yu Wu 电子研究所 |
关键字: | 细胞非线性网路;比例式记忆细胞非线性网路;联想记忆体;细胞非线性网路通用机器;大邻近层细胞非线性网路;Cellular nonlinear network;Ratio-memory cllular nonlinear network;Associative memory;Cellular nonlinear network universal machine;Large-neighborhood cellular nonlinear network |
公开日期: | 2002 |
摘要: | 本论文的主旨在于阐述细胞非线性网路架构之分析与设计及其在联想式记忆体及图像辨识上之应用。论文中包含下列三个主要部分: (1) 以双载子接面电晶体乘除法器架构之比例式记忆细胞非线性网路之分析与设计; (2)含自我回授之键值之新型细胞化非线性网路的设计; (3)大邻近层细胞非线性网路通用机器之概念设计。 首先,本论文中提出并分析一个用来制作超大积体电路神经网路系统的新型紧密双载子接面电晶体乘除法器之架构,在这个新型的四象限乘法及二象限除法电流模式电路中,利用互补式金氧半制程中的寄生PNP双载子接面电晶体之射极电流与基极射极间电压呈指数关系来实现乘除法器。该乘除法器之的架构同时能被用来产生比例式键值并将该键值与对应之其它神经元输出相乘,因此,这个双载子接面电晶体乘除法器具有小的晶片面积与架构密集的优点,同时这个双载子接面电晶体乘除法器已经成功的被应用来实现类比式联想记忆体。这个类比式联想记忆体网路能够储存多套的图案样本,此外,还可将带有杂讯之图像样本辨识并还原回原来所习得之样本。我们以0.35微米互补式金氧半制程技术设计与制作了一个具有9x9细胞阵列大小的比例式记忆类比细胞非线性网路晶片,模拟与实验已经成功地验证了这个9x9细胞阵列大小的双载子接面电晶体神经元架构之类比细胞非线性网路。 其次,根据这个双载子接面电晶体乘除法器所架构之原始比例式记忆细胞非线性网路,我们提出并分析一个新型比例式记忆之细胞非线性网路架构。在这新型的比例式记忆细胞非线性网路中,模版A之自我回授键值及被导入。另外不同于原始比例式记忆细胞非线性网路将所有绝对键值的绝对值相加来当比例式键值的分母,新型之比例式记忆细胞非线性网路简化为直接取最大绝对值来当分母。虽然两者略有不同,但就观察模拟的结果,新型比例式记忆细胞非线性网路依旧保有增强习得样本特征的能力。对于新型之比例式记忆细胞非线性网路,其模拟结果显示可习得18x18样本个数达98个。而在杂讯程度为0.3的状况下,即使学习98个样本,其辨识率仍可达86.9%。 最后,我们提出并分析另一个具有大邻近层数不对称模版的新型细胞非线性网路通用机器架构。在传统的细胞非线性网路通用机器中,仅单一邻近层的键值可以被实现。此乃因受限于二维的制程无法实现大邻近层等复杂的键值。而利用非直接连接之神经键,我们可以实现相当于大邻近层细胞非线性网路的功能而不需要再额外连接大邻近层的键值。三个大邻近层细胞神经网路在杂讯消除、联接物侦测与箭头幻觉等正确的功能已经由软体模拟成功的验证。 经由模拟与实验的验证,本论文所发展出的以双载子接面电晶体乘除法器架构成之比例式记忆细胞非线性网路对于设计字元辨识系统之单一晶片系统具有极大的潜力,而大邻近层细胞非线性网路之设计则简化了大邻近层连线的复杂度。未来将朝上述领域继续研究;并把联想记忆体之比例式记忆功能整合于细胞非线性网路通用机器此一类比平行影像处理系统中。 In this thesis the new analog cellular nonlinear(neural) network structure with ratio memory and the cellular nonlinear(neural) network universal machine are designed and analyzed. The main parts of this thesis include: (1) the analysis and design of the cellular nonlinear(neural) network with ratio memory structure and the applied to the implementation of the analog associative memory; (2) the design of new ratio memory cellular nonlinear(neural) networks structure with self-feedback weight of template A; (3) the conceptual design of the new Cellular Nonlinear(Neural) Network Universal Machine with programmable large-neighborhood asymmetric templates. Firstly, the new elements, called analog current mode four-quadrant multiplier and two quadrant divider, which is applied in the ratio memory cellular nonlinear(neural) network for the compact implementation of VLSI neural network is proposed and analyzed. In the new element structure, the parasitic PNP Bipolar Junction Transistor (BJT) in the CMOS process is used to implement the multiplication and division. It utilizes the exponential relationship between the emitter current and the base-emitter voltage of parasitic PNP Bipolar Junction Transistor (BJT). Using this relation, both multiplication and division can be realized in a simple BJT structure. The BJT-based multiplier-divider has the advantages of compact structure and small chip size. The BJT-based multiplier-divider has been successfully applied to the implementation of the analog associative memory. The analog associative memory can store many sets of exemplar patterns. Moreover, the input patterns can be recognized and recovered to the correct patterns. An experimental chip of the proposed neuron-bipolar junction transistor (□BJT) analog associative memory with the cell size of 9x9 has been designed and fabricated by using 0.35 µm single-poly quadric-metal (SPQM) n-well CMOS technology. The analog associative memory has been successfully verified through both simulation and measurement in the ratio memory cellular nonlinear(neural) network with the sizes of 9x9. With simple and compact structure and high integration capability, the proposed BJT-based multiplier-divider has a great potential in the VLSI implementation of neural network. Secondly, based on the basic ratio memory cellular nonlinear(neural) network for associative memory, a new ratio memory cellular nonlinear(neural) networks (RMCNN) structure called the SRMCNN are proposed and analyzed. In the new RMCNN, the self-feedback weight of template A is applied for enlarge the numbers of stored patterns. Except the above additional templates, the learning algorithm is also a little different from the original RMCNN. In the new RMCNN, the denominator of the ratio weight is simplified to be the maximum absolute value of the absolute weight instead of the sum of the absolute value of the absolute weights. Thus, the sum circuit can be eliminated. Though the learned weights of the new RMCNN is different from the original RMCNN, the software simulation results display that the new RMCNN still keep feature enhancement. Furthermore, the new RMCNN can recognize and recover more patterns than the original RMCNN. The new RMCNN can learn up to 98 patterns. In the case of noise variance level being 0.3, the recovery rates of the new RMCNN is still up to 86.9%. Finally, the new cellular nonlinear(neural) network universal machine (CNNUM) structure with asymmetric templates and large-neighborhood is proposed and analyzed. In conventional CNNUM, only the single-neighboring cells are connected to the cell. It is because that the 2D CMOS technology limits the implementation of large-neighboring or complicated interconnections. Indirect connection used in the LN-CNN makes it being possible to implement the large-neighborhood templates without extra direct large-neighboring interconnections. As the demonstrative examples on the applications of the proposed large-neighborhood CNN, three functions of noise removal, connected component detection, and Muller-Lyer arrowhead illusion have been successfully realized and verified by software simulation with the corresponding templates. From the above results, it is believed that the proposed RMCNN structure and its application on pattern recognition have a great potential in system-on-a-chip design of the neural network systems, and the proposed LN-CNNUM structure can simplify the complex of the large-neighborhood interconnections. Further researches in the two fields will be conducted in the future, and the ratio memory structure will be embedded into the analog parallel image processor. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT910428162 http://hdl.handle.net/11536/70492 |
显示于类别: | Thesis |