微小化面積 里德-所羅門 解碼器之設計與實現

Abstract

在本篇論文當中，我們提出了一個微小化面積的里德-所羅門(Reed-Solomon)解碼器架構。對於t個改錯能力的里德-所羅門碼，我們只需使用t+1個有限場(finite field)乘法器即可完成inversionless Berlekamp-Massey演算法當中的錯誤位置多項式(error location polynomial)運算，相較於其他相關的研究，此一設計可以節省30％至80％的面積。將此一架構最佳化之後，關鍵路徑(critical path)為一個有限場乘法器加上一個有限場加法器再加上兩個雙埠多工器(2×1 multiplexer)。在TSMC的0.25μm製程與SYNOPSYS軟體下的模擬環境下，我們針對(255,239) 里德-所羅門碼所合成出來的錯誤多項式更新方塊(error location update block)只需要16043個邏輯閘。並且在Debussy軟體中的波形模擬環境下，錯誤多項式更新方塊可在274Mhz的運作時脈下正確運作。

This paper presents a small-area architecture for Reed-Solomon decoder. For t error correct capability Reed-Solomon code, the architecture just needs t+1 finite field multiplier for error location polynomial computation, which is base on inversionless Berlekamp-Massey algorithm. Compare with other research about Reed-Solomon decoder, this architecture will save 30% to 80% area. The critical path of this architecture passes through one finite field multiplier, one finite field adder, and two 2x1 multiplexer. For (255,239) Reed-Solomon code, the complexity of the error location update block reported by synthesis tool in SYNOPSIS was 16043 gates in TSMC’s 0.25μm CMOS technology. And the error location update block can operate at 274Mhz correctly in Debussy’s waveform simulation tool environment.