MIMO-OFDM收發機之FPGA實現

Abstract

近年來，OFDM在新一代無線通訊系統的發展上佔有相當關鍵性的地位，它採用快速傅利葉轉換做為調變技術以提升系統頻寬使用效益，並利用插入保護區間，以有效解決多路徑效應產生的碼間干擾。在本論文中，吾人利用Aptix® MP3C可重組系統平台，實現MIMO-OFDM系統軟硬體架構，該平台整合了FPGA、DSP及部分類比元件模組。其中，FPGA為可程式化之邏輯元件，利用硬體描述語言合成數位邏輯電路，具有可重構性之特性，提供快速之硬體驗證。而DSP則擁有高速之浮點及定點運算，可用以實現即時的訊號處理。本論文的重點在以FPGA實現MIMO-OFDM收發機架構中之粗略時序同步、精確時序同步，離散傅利葉轉換，及自動頻率控制器等區塊，完成系統同步之功能。吾人進一步導入軟體無線電之概念，在上述硬體電路之設計上予以模組化，以增加系統之擴充性及可適性。

In recent years, OFDM has become a key technology in the development of new wireless communication systems. It can increase the bandwidth efficiency by utilizing the Fast Fourier Transform as it’s modulator and uses guard interval to combat the inter symbol interference caused by multipath fading. In this thesis, we will realize the MIMO-OFDM baseband transceiver on the Aptix MP3C reconfigurable system platform, which integrates FPGA, DSP and some analog devices. FPGA is a programmable logic device which can be used to design digital logic circuits by hardware description language and provide fast hardware verification based on its reconfigurability. On the other hand, DSP is a powerful processor with high speed floating-point or fixed-point operations, which is suitable for real-time signal processing. In this thesis, we will focus on the realization of MIMO-OFDM transceiver by FPGA, which includes a coarse time synchronizer, a fine time synchronizer, a Discrete Fourier Transform circuit and an auto frequency controller. Together these form the synchronization part of the system. With the concept of software-defined radio incorporated, we can increase the scalability and adaptivity of the system by modulizing the above mentioned hardware circuits.