寬頻分碼多重擷取系統之快速碼擷取架構及其FPGA實現

Abstract

這篇論文的主要目的是設計及硬體實現一個上鏈(uplink)通道寬頻分碼多工擷取(W-CDMA)系統的快速碼擷取(fast acquisition)系統。在寬頻分碼多工擷取系統中，實體隨機擷取頻道(PRACH)的前序碼(preambles)通常被使用作為傳輸初始同步的動作。由於特殊的前序碼結構，傳統匹配濾波器(matched filter)碼擷取架構需要很高的計算複雜度。在本篇論文中，吾人使用快速哈達馬轉換(Fast Hadamard Transform)來解決這個問題。在同樣的碼擷取效能上，快速哈達馬轉換能顯著的減低碼擷取系統中的計算複雜度。另外我們也使用雙重區塊(double dwell)搜尋技術來降低錯誤通報(false alarm)的機率。模擬的結果顯示出我們的設計在低訊雜比的環境中也能有很高的擷取正確機率。最後我們使用VHDL硬體描述語言與Xilinx FPGA的設計流程來實現我們設計的系統。

The purpose of this thesis is to design and implement a fast acquisition system for W-CDMA uplink transmission. In W-CDMA systems, preambles of the PRACH (physical random access channel) are used for initial synchronization. Due to the special preamble format, the conventional matched-filtering acquisition scheme requires high computational complexity. In this thesis, we employ a fast Hadamard transform (FHT) approach to solve the problem. While achieving the same acquisition performance, the FHT can significantly reduce the complexity of the acquisition system. To reduce the false alarm probability, we also use a double-threshold detection scheme. Simulations show that our design has high acquisition probability in low signal to noise ratio environment. Finally, we implement the system using VHDL hardware description language and the Xilinx FPGA design flow.