數位航空接收機之硬體設計及FPGA實現

Abstract

由於航空交通量大幅增加，傳統飛航裝備與系統漸不符合民航界需求，特高頻的飛機通訊定址與回報系統(ACARS)雖然目前廣泛被使用，但其位元傳輸率偏低，通訊容量小已不敷航空通訊應用內容與數量之用。因此，國際民航組織(ICAO)等組織便制訂了一套新的航空通訊系統，特高頻數位鏈結(VDL)，其數據傳輸率高且通訊容量大將取代 ACARS，成為下一代陸空通訊的主流。 本論文之目的在於設計VDL第2模式的基頻接收機並做效能之模擬分析，首先我們建立了航空的通道模型，可以有效的模擬空中和地面的通道，而在設計基頻電路時，根據通道模型我們考慮了其特性，如多重路徑延遲、都卜勒效應等等。為了有效的接收訊號，我們將設計下面幾種元件：匹配濾波器、時序回覆電路、頻率偏移估測裝置和決策回饋等化器。本論文採用Matlab來進行整個接收機的系統模擬和效能分析，結果顯示我們所設計的接收機可在惡劣的通道下達到VDL的要求。最後，我們試著對整個接收機裝置，設計低複雜度的硬體架構，並以FPGA作硬體實現。本論文之結果可提供初步的接收機架構雛型，以協助建立國內下一代陸空通訊系統的關鍵技術。

The currently used air-ground communication system is the Aircraft Communication Addressing and Reporting System (ACARS). Due to its low data transmission rate and small communication capacity, ACARS cannot cope with the need for the high throughput aeronautical communication. Thus, ICAO embarked on definition of a new standard for aeronautical communication. This is the VHF digital link (VDL); it has higher transmission rate and large capacity. The VDL will gradually replace the ACARS and become the key VHF data link system for the next generation air-ground data communication. This thesis is aimed to design a VDL mode2 basedband receiver and analyze its performance. First, we establish an aeronautical model, which can effectively model the air-ground channel. Based on the channel characteristics, we design key receiver modules including the matched filter, the timing recovery circuit, the frequency offset estimator, and the decision feedback equalizer. We then build a receiver model and use MATLAB to simulate its performance. The simulation results show that the designed receiver can meet the VDL requirement even in a harsh channel condition. Finally, we design a low-complexity receiver architecture and implement the receiver using FPGA. The result of this thesis can be further enhanced to build a complete VDL mode2 transceiver and be used to establish the key technology for the next-generation air-ground communications.