完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 羅仁聰 | en_US |
dc.contributor.author | Ren-Chon Luo | en_US |
dc.contributor.author | 周長彬 | en_US |
dc.contributor.author | 吳文發 | en_US |
dc.contributor.author | Chang-Pin Chou | en_US |
dc.contributor.author | Wen-Fa Wu | en_US |
dc.date.accessioned | 2014-12-12T02:31:17Z | - |
dc.date.available | 2014-12-12T02:31:17Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT910489051 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/70806 | - |
dc.description.abstract | 隨著極大型積體電的迅速發展,元件尺寸已進入次微米的領域,電容、電阻時間延遲及訊號干擾等問題日益嚴重。為了改善此問題,以極低介電常數材料取代傳統二氧化矽作為導線間的絕緣層就成為必要的選擇。 本研究首先在於改善低介電材料熱穩定性不佳的缺點。當薄膜受熱超過350℃,本身矽烷鍵結會有部分斷裂,而產生吸水問題,使得介電常數上升,但當再經過一次表面改質後,介電常數又可降低,其值甚至比未熱處理過的試片來的低,推測是由於第二次表面改質時會於薄膜上形成更為緻密的矽烷群,而使其抗水效果增強。 非晶相氫碳化矽(a-SiCx:H)於低介電材料上的覆蓋研究結果,以操作條件:ICP power為500W、溫度為100℃較佳。因為較大的電漿功率所沉積的Si-C較多,氫含量亦較多,而使介電常數降低,但抗水性會較差。氫碳化矽/低介電薄膜經熱處理後,整體介電常數亦會上升。但經由疏水改質,介電常數又可降低,但須注意接合面的氣化問題,會造成薄膜表面粗糙度受損。 在低介電材料和金屬的熱應力循環探討部分,本實驗結果顯示低介電薄膜所含的殘留應力值約為200Mpa,應為旋轉塗佈及高溫固化時所殘留。低介電材料和阻障金屬(Ta或TaN(5%))的熱應力探討則以TaN有較小的應力值,而和Ta的接合性較好。銅於約280℃會有晶粒成長現象,塑性變形亦於此溫度產生。 | zh_TW |
dc.description.abstract | As the rapid development of ULSI, the IC device is moving into the sub-micron scale. The performance of integrated circuits will be significantly limited by the interconnect RC time delay . To alleviate this impact, using ultra low dielectric constant to replace traditional silicon dioxide as the insulator dielectric layer has become the unavoidable choice. This study discussed the thermal stability of low-k film, and solved the problem of poor thermal stability. As the thermal temperature is higher than 350℃, the Si-alkyl on the surface will be degenerated and causes the increase of dielectric constant . If the film is modified by hydrophobic treatment, the k value will come down and even be lower than that of deposited film. This is due to the increase of dense Si-alkyl group on the surface and the moisture resistance is increased. From the experimental results of a-SiCx:H deposited on the low-k film, the better operation condition is ICP power :500W, temperature:100℃. The higher plasma power can produce more Si-C content and the H content, therefore the dielectric constant will be decreased, but the moisture resistance will be reduced. After 400℃ and higher heat treatment, the total dielectric constant will be increased. After modification by hydrophobic treatment, the k value can be reduced. However, in hydrophobic treatment, the problem of gasification must be noticed since it will cause the higher roughness of the surface. After the study of the thermal cycling, the residual stress of the low-k film was found about 200 MPa and it may be caused by the spin coating and high temperature solidification. The thermal stress value of TaN(5%) barrier is lower than that of Taand Ta has the better adhesion. In the copper film, there will be grain growth at about 280℃, and the plastic deformation is occured at this temperature. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 低介電材料 | zh_TW |
dc.subject | 熱處理 | zh_TW |
dc.subject | 表面修飾 | zh_TW |
dc.subject | HMDS | zh_TW |
dc.subject | 可靠度 | zh_TW |
dc.subject | low dielectric constant matreial | en_US |
dc.subject | heat treatment | en_US |
dc.subject | surface modification | en_US |
dc.subject | HMDS | en_US |
dc.subject | reliability | en_US |
dc.title | 多孔性低介電材料與金屬導線之整合與探討 | zh_TW |
dc.title | Integration and Study of Porous Low Dielectric Constant Material and Metal Interconnect | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 機械工程學系 | zh_TW |
顯示於類別: | 畢業論文 |