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dc.contributor.author林盟淳en_US
dc.contributor.authorMeng-Chuen Linen_US
dc.contributor.author董蘭榮en_US
dc.contributor.authorLan-Rong Dungen_US
dc.date.accessioned2014-12-12T02:31:36Z-
dc.date.available2014-12-12T02:31:36Z-
dc.date.issued2002en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT910591024en_US
dc.identifier.urihttp://hdl.handle.net/11536/71009-
dc.description.abstract中值濾波器在一維語音與二維影像處理扮演一個很重要的角色,中值濾波器利用其非線性的運算可以把脈衝雜訊訊給移除掉且不影響鄰近的訊號特性。本篇論文採用最多數決方式的中值濾波器演算法,並據以提出新式的一維/二維中值濾波器之實現方法。本論文提出的方法是以DCAM (Dual Content Addressable Memory)及多數決電路為基礎設計出可由使用者彈性實現一維或二維中值濾波器的DCAM 處理器。在晶片製作上,我們額外加入了掃描測試電路對敏感的多數決電路進行測試。晶片的實現面積為2401.9×2401.9 mm2,共7648個電晶體。根據模擬結果,當操作頻率為100MHZ時,DCAM 處理器足以適用於一維語音處理之應用,同時對二維影像處理方面而言,可以即時處理MPEG-1影像格式。zh_TW
dc.description.abstractMedian filtering plays an important role in modern signal processing applications in that it can perform filtering operations in statistical. The nature of nonlinearity makes median filtering a perfect tool to remove impulsive noise for audio or image processing applications. This thesis proposes a novel 1-D/2-D median filter architecture that consists of a DCAM (Dual Content Addressable Memory), a clocked majority circuit, and filtering controllers. The DCAM features a dual-field CAM structure that cooperates with maskable search/write registers for parallel operations. For the purpose of verification, we realize the proposed architecture into two parts: DCAM processor and function controller. The DCAM processor is implemented as an ASIC, and the function controller is prototyped by using FPGA. As the results, the die size of DCAM processor is 2401.9× 2401.9 mm2 and can process MPEG video in real-time while being operated at 100 MHz.en_US
dc.language.isozh_TWen_US
dc.subject雙內容可定址記憶體zh_TW
dc.subject中值濾波器zh_TW
dc.subjectDual-CAMen_US
dc.subjectDCAMen_US
dc.subjectMedian Filteren_US
dc.title以雙內容可定址記憶體為基礎之一維/二維中值濾波器設計zh_TW
dc.titleA Dual-CAM based 1D/2D Median Filter Designen_US
dc.typeThesisen_US
dc.contributor.department電控工程研究所zh_TW
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