四階數位放大器之FPGA硬體平台實現

Abstract

Recent advances in logic devices and digital signal processing have allowed a digital amplifier to become a reality. Audio amplifiers based on Class-D topology offer more advantages for portable audio applications, in terms of size, efficiency and cost, than the traditional Class-A or -AB type. Class-D amplifiers commonly rely on Pulse-Width-Modulation (PWM) to generate the output switching waveform, despite consequent problems such as high switching losses and harmonic distortions. A more effective technique to implement the Class-D Amp is thru the Sigma-Delta algorithm. The goal of this research is to investigate the issues involved in the design and implementation of the Sigma-Delta Modulator (SDM). Such modulator is of particular interest due to its ability to shape the quantization noise floor of low resolution quantizers, moving a majority of the quantization noise to a high frequency range, increasing the low frequency dynamic range of the converter. This noise shaping is achieved through feedback loops, and multiple loops can be combined to improve the noise shaping effect. Even though sigma-delta modulation has become a widespread method of analog-to-digital conversion, its operation has not been completely defined. The majority of the analysis carried out on the circuit has been from a linear standpoint, despite the fact that the SDM itself is a non-linear system. Unfortunately, the linear model breaks down when white-noise assumptions fail to hold, causing stability and limit-cycle problems in higher-order modulators. This thesis provides an approach to obtain and optimize the stable feedback coefficients for higher-order one-bit SDMs. Scaling techniques have been widely applied in the designs of□SDMs to save power consumption. It is well known that the scaling coefficients should be properly chosen so that the scaling operation does not cause significant degradation of the Signal-to-Noise Ratio (SNR) performance. This thesis presents guidance for selecting scaling coefficients and introduces a novel 1.5-bit architecture in order to minimize power consumption while maximizing modulator performance. Theoretical models for a 4th-order low-pass modulator and an 8th-order band-pass modulator have been developed and simulated in MATLAB. Hardware descriptions have been made in VHDL for realization in FPGA. Simulations of the MATLAB-code and the VHDL-code give identical results. The design is synthesized in MAX+PLUS II environment and downloaded into an FPGA, namely Altera FLEK10K EPF200S. With peripheral interfaces such as Enhanced Parallel Port (EPP) or Universal Serial Bus (USB), a fully digital audio communication path is provided, from signal input to amplifier output, with the loudspeaker being the only analog component.