金線密度對偏移之影響分析

Abstract

現今電子產品多以朝向輕、薄、短、小與多功能趨勢發展，使得IC元件薄小化成為必要的發展技術，除了IC製程技術突破，提供晶片保護並作為訊號傳輸媒介的IC封裝技術也必須隨之跟進，對於金線偏移的預測與控制便是一例。當元件尺寸越小I/O數越高的情況，金線偏移量所引發的問題就漸漸浮上台面，成為封裝所必須克服的技術關鍵，其中以數值模擬預測並透過修正製程參數或模穴設計改善金線偏移情況，便是一快速並節省成本的方法。 本研究參考過去的文獻中所提出的金線偏移計算方法，針對高密度金線封裝提出一套可行的計算流程。另仿造過去傳統的金線偏移分析方法，計算不同金線分佈下的偏移量，與本研究中提出的金線偏移分析方法所得到的結果比較，討論不同金線密度下金線偏移情形。

Because the electric products trend to become lighter, thinner, smaller and multi-functional, semiconductor industry has to focus on IC chip scale-down. Meanwhile, IC packaging technology must also become more advanced to be compatible with this trend. Wires weep is one of the important issues in packaging technology. With the size-decreased chips and the number-increased I/Os, the problems due to wire sweep become more and more serious and often reduce the yield of products; so to control the amount of sweep within an acceptable range become one of the key points in advanced packaging technology. Currently, the most cost effective solution to predict and correct wire sweep is to use numerical simulation to obtain the optimum process parameters and mold cavity design. A new simulation scheme for wire sweep analysis evolved from traditional methods was be discussed in this research. A comparison of results from both simulation methods was conducted for different wire distribution densities. The change of the wire sweep behavior according to the wire distribution density was concluded and discussed.