完整後設資料紀錄
DC 欄位語言
dc.contributor.author陳律璋en_US
dc.contributor.authorLu-Chang Chenen_US
dc.contributor.author鄭晃忠en_US
dc.contributor.authorHuang-Chung Chengen_US
dc.date.accessioned2014-12-12T02:32:11Z-
dc.date.available2014-12-12T02:32:11Z-
dc.date.issued2002en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT911706008en_US
dc.identifier.urihttp://hdl.handle.net/11536/71304-
dc.description.abstract隨著半導體製程技術的演進,元件尺寸也越來越小,因此,離子植入的方式漸漸驅向於低能量、高劑量來形成較淺接面,以符合需求。而電路構成的基本元件 --- 金氧半電晶體,其閘極氧化層的厚度也越來越薄(小於100 angstroms)。因此,對於離子植入時所帶來的表面電荷對於元件電性的影響也日亦嚴重。 本篇論文主要探討在低能量、高電流時的離子植入對元件電性的影響,以及如何利用負電子產生機制來產生足夠的電荷,用來達到晶片表面電性的平衡,避免閘氧化層因電荷累積效應而導致元件崩潰而影響電性表現,並且,試圖找出佈植電流和表面電性中和所需電子量之間的比例關係,以求得正常工作的元件電性表現。 本次研究,從離子佈植電流的寬度、電流密度與負電荷之間的關係及變化開始,利用之間的變化情形,分別從兩方面來探討: 一方面在控片上的影響,另一方面在實際金氧半電晶體元件上電性參數的表現。這次實驗結果顯示,在控片上的差異並不明顯,但是在金氧半電晶體元件的電性參數測量上,卻有顯著的差異,其原因為光阻的存在,對植入的離子在表面上的累積現象,有一定程度的貢獻。另外,對於金氧半電晶體的氧化層,在不同的負電荷數量條件,以及不同的氧化層厚度(28、48 和 70 angstroms)下,表面電荷的累積現象和閘氧化層崩潰與起始電壓的變化關係亦有所描述。zh_TW
dc.description.abstractDuring the semiconductor technology improvement, the device dimensions is shrinking, or its use as a backup for high current and low energy applications to form the ultra shallow junction for requirement. The fundamental device --- MOSFET, further advancement in device design imposed a need to minimize the wafer charging down to a few volts due to the use of thin gate oxide less than 100 angstroms thickness. This thesis is to study the influence of the device electronic properties performance in low energy, high current ion implantation. And how to use plasma flood gun system to generate enough electrons to neutralize the surface charges in balance situation, which could prevent the gate oxide breakdown by surface charge accumulation effect. Try to find the correlative with the process beam and plasma flood gun current, which could get the normal electronic properties. Original from the relationship with process beam current width, current density and the plasma flood gun current in this study. From two ways to discuss this difference: one is the influence in bare wafers and the other is in MOS devices to demonstrate the electronic properties. The experimental results show the photoresist will trap the charge to let the threshold voltage and breakdown voltage shift. Breakdown voltage measurement for MOS devices with various gate oxide thickness (28、48 and 70 angstroms) by Boron ions implant with various plasma flood gun current conditions, and the relationship will be described.en_US
dc.language.isoen_USen_US
dc.subject離子植入zh_TW
dc.subject表面電荷效應zh_TW
dc.subject閘氧化層zh_TW
dc.subject崩潰電壓zh_TW
dc.subject硼離子zh_TW
dc.subject低能量zh_TW
dc.subjection implantationen_US
dc.subjectsurface charge effecten_US
dc.subjectgate oxide layeren_US
dc.subjectbreakdown voltageen_US
dc.subjectBoron ionsen_US
dc.subjectlow energyen_US
dc.title低能量離子植入的表面電荷效應之研究zh_TW
dc.titleStudy of Surface Charge Effect In Low Energy Ion Implantation Processen_US
dc.typeThesisen_US
dc.contributor.department電機學院電子與光電學程zh_TW
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