具奈米級通道寬度之矽化鈷蕭特基障位的複晶矽薄膜電晶體研究

Abstract

在這篇論文中，我們提出並驗證了一種新型的poly-Si TFT元件，此元件具有奈米級Fin (鰭狀)通道、金屬矽化物形成的源/汲極及以Sub-gate 感應出來的源/汲 極延伸區。這Fin 通道是由as-deposited LPCVD poly-Si 形成的，並且被main-gate 由上部及兩邊包起來，形成所謂 “tri-gate” 結構。這種結構能有效抑制汲/源 極之間的漏電流，並且對短通道效應的控制能力也大大被改善。 新元件展現了優異的雙向 (n 通道及p通道 )次起始( subthreshold)特性，即陡斜之次起始斜率(subthreshold slope)及高的開/關 電流比值。對於sub-gate扮演之角色，它不僅能提升導通電流，更能抑制漏電流。有關poly-Si FinFETs 與先前學長( F.J.Hou) 提出SOI FinFETs 之間的差異，也將在這篇論文中討論。

In this thesis, we proposed and demonstrated a novel poly-Si TFT device with nano-scale fin-like channel featuring silicide source/drain and electrical junction induced by a sub-gate configuration lying over the passivation dielectric. The fin-like channel, which is consisted of as-deposited LPCVD poly-Si material, is surrounded on three sides by the main-gate, forming the “tri-gate” configuration. The drain-to-source leakage current can thus be effectively suppressed. Moreover, the controllability of short-channel effects is also significantly improved. The fabricated devices show excellent ambipolar subthreshold characteristics with steep subthreshold slope and high on/off current ratio. It is also shown that the application of sub-gate bias can not only increase the on-current, but also reduce the off-state leakage. Differences in device characteristics between poly-Si FinFETs fabricated in this study and the SOI FinFETs previously reported by a senior classmate (F. J. Hou) are also discussed in this thesis.