標題: | 電子束鄰近效應的校正與具鰭狀通道之SOI場效電晶體 E-Beam Proximity Effect Correction and Its Application to the Fabrication of SOI FinFET |
作者: | 劉正財 Jan-Tsai Liu 黃調元 林鴻志 Tiao-Yuan Huang Horng-Chih Lin 電機學院電子與光電學程 |
關鍵字: | 電子束鄰近效應的校正;鰭狀通道場效電晶體;E-Beam Proximity Effect Correction;FinFET |
公開日期: | 2002 |
摘要: | 積體電路發展至今已超過四十年,由演進歷史來看,每2-3年積體電路的集積度增加四倍,這與光學微影發展有密切關聯。但近來光學微影發展面臨到阻礙,如曝光波長及景深的限制。為了克服這些困難,不僅是對如何改善光源波長,同時針對具高解析度能力的電子束及X-ray微影技術亦被廣泛地探討。電子束直寫微影成為最具有高解析度候選人之一,被應用到積體電路製造時,具有節省大量光罩費用的優勢。但低產出(throughput)與鄰近效應(proximity effect)控制是其發展上的最大問題。
本篇論文主要研究電子束鄰近效應的校正,及應用於元件的製造。電子束鄰近效應是由於電子束射入阻劑時,在阻劑與底材界面引起的電子散射所造成。為了獲得圖案的真確性,需對鄰近效應進行修正。本研究關於鄰近效應的參數萃取,係藉由甜甜圈法獲得,並帶入商業軟體PROXECCO執行曝光強度分佈函數調整,使得鄰近效應獲得良好的校正。在元件的製作上,我們使用電子束直寫系統及NEB22-A4電子束阻劑,曝出奈米鰭狀通道(fin channel)與閘極圖案,同時驗證NEB22-A4電子束阻劑具有高深寬比,小線寬成像,及低劑量等優點.
我們已經成功地製造具鰭狀通道之SOI場效電晶體(FinFET)。通道長度為140 nm 與鰭狀通道為60 nm的元件其次臨界擺幅(subthreshold swing)約為80 mV/dec. 在 Vds = Vgs = 2V 時的驅動電流可達230 mA/mm。實驗上也發現,製程熱預算(thermal budget)的控制也將明顯影響元件的短通道效應(short-channel effect)控制。 Integrated circuit (IC) technology has been advanced significantly over the last 40 years. The steady progress is critically dependent on the development of optical lithography. However, optical lithography is now facing a number of challenges for generating extremely fine patterns. In addition to the optical solution, electron-beam (e-beam) lithography is one of the promising alternatives for high-resolution patterning. In this thesis, we study and address the proximity effect that is an important issue in e-beam lithography. This effect is due to electrons scattering in the resist and the underlying material. To achieve pattern fidelity, the proximity effect must be corrected. The proximity’s parameters are extracted from the doughnut method and substituted into a commercial software, PROXECCO, to modulate the dose intensity distribution for good proximity effect correction. For device fabrication, the patterns of nano-scale fin-channel and poly-Si gate were generated using an e-beam direct writing system. NEB22-A4 negative electron resist was used since it has been characterized and demonstrated to possess several advantages including high contrast, high aspect ratio, sharp line edge in fine lines, and lower dosage. We have also successfully fabricated FinFETs on SOI wafers by using the developed e-beam exposure method and correction technology. Devices with channel length and fin width of 140 nm and 60 nm, respectively, have been successfully fabricated in this study. The fabricated devices exhibit subthreshold swing of around 80 mV/dec, and saturation drain current of 230 mA/mm at VDS = VGS = 2V. Our results also show that the RTA process used in the fabrication may seriously affect the devices’ controllability of the short-channel effects. Special attention should thus be paid to carefully control the process thermal budget for further miniaturization of the device dimension. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT911706026 http://hdl.handle.net/11536/71319 |
顯示於類別: | 畢業論文 |