應用於三維立體高畫質影像之三維動態記憶體 堆疊模型建造及管理單元

Abstract

在多媒體通訊系統裡，三維立體影像技術無可避免地將成為未來的主流。隨著三維立體高畫質影像解析度的提升，需要更高的記憶體存取頻寬以及更大的容量來處理龐大的影像資料。然而，傳統隨機存取記憶體(DRAM)因為腳位數量的限制而無法使頻寬有效的提升。鑒於這原因，在本論文中，我們提出了三維動態記憶體堆疊模型的建造以及其低功率階層式記憶體管理單元的設計以解決上述問題。 利用矽導孔(TSVs)技術的三維動態記憶體堆疊比起傳統的隨機存取記憶體多出至少32倍的輸入/輸出腳位。所提出之4Gb容量，四層推疊架構的三維動態記憶體模型，在333MHz的外部頻率下頻寬最高可以達到21.3GB/s。另外，所設計之應用於三維立體影像深度圖計算的階層式記憶體管理單元，利用指令的重新分配以及依據資料特性的區塊交錯存取機制，可以節省約54.3%的頻寬。在功耗方面，所提出之可依照溫度變化調控刷新(refresh)時間的感應機制，以及可調式深沉省電模式下，至多可以減少43.46%的能量消耗，以達到低功高效能的最佳記憶體使用率。

In multimedia communication systems, 3D video technology is inevitably a major trend in the future. With the increasing resolution of 3D high definition (HD) video, high bandwidth of memory accesses and large capability of storage are required for these mass video contents. However, bandwidth of conventional DRAMs cannot be increased by the limited I/O pins. In view of these, a 3D-Stacked DRAM modeling and the corresponding low-power hierarchal memory management unit (MMU) are designed implemented for 3D HD video in intelligent multimedia communication systems. Based on the through-silicon-vias (TSVs) in 3D-stacked DRAM, the I/O pins between logic tiers and DRAM are 32x at least compared to conventional DRAMs. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with TSVs, the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator and local slice/global rank controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can realize the bandwidth improvement by 54.3% through the command reordering and bank/rank interleaving. Moreover, the power reduction can be achieved up to 43.46% at low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.