應用於植入式醫療系統單晶片之互補式金氧半低功率整數型串接式鎖相迴路之研製

Abstract

近年來植入式的生醫元件在醫學治療上漸漸受到重視，1999年美國聯邦通訊委員會為了植入式通訊元件而訂定MICS (Medical Implant Communication Service)頻段。2009年更擴展其頻段，做為診斷與治療為目的的植入式醫療元件使用，更名為MedRadio (Medical Device Radiocommunications Service)。 本篇論文提出一個提供載波與時脈訊號的低功率串接式鎖相迴路給一含MedRadio收發機，類比數位轉換器，數位訊號處理器和13.56-MHz無線電源供給的系統單晶片。所提出的串接式鎖相迴路，第一級提供取樣時脈而第二級提供載波時脈。再者，接收無線功率傳輸系統的線圈被用來當作13.56-MHz 的參考訊號，以及使用環形電壓控制振盪器來降低功率消耗與減小面積。 此晶片以台灣積體電路股份有限公司0.18微米製程設計與實現，根據量測結果證實，此鎖相迴路輸出頻率為402.9MHz並展現了相位雜訊-79 dBc/Hz在離中心頻率100kHz位移處。結果顯示兩個串接的鎖相迴路工作良好，且在系統操作電壓為1.8V，第一級鎖相迴路只消耗 0.28mW，第二級鎖相迴路消耗0.46mW，面積0.525mm2。 所提出的串接式鎖相迴路擁有低功率消耗，小晶片面積以及沒有晶片外的元件與石英震盪器。因此此晶片適合整合在植入式的醫療系統單晶片中。最後本論文探討，兩級同時啟動時，抖動量測不佳的原因並予以改善。

In recent year, the implanted biomedical devices are got more and more attention in medical treatment. The Federal Communications Commission (FCC) announced the MICS (Medical Implant Communication Service) band for the implanted communication devices in 1999. In 2009, the band was broadened and renamed as MedRadio (Medical Device Radiocommunications Service) for diagnostic and therapeutic purposes. In this thesis, a low power integer-N cascaded phase locked loop (PLL) is presented to provide the carrier signal and clock signals for a SOC with MedRadio-band transceiver, ADC, DSP, and 13.56-MHz wireless power supply. In the proposed cascaded PLL, the first PLL provides the sampling clocks while the second PLL provides the carrier clock. Furthermore, the 13.56-MHz signal from the receiving coil of the wireless power transmission system is utilized as the input reference signal. Ring-based voltage controlled oscillator (VCO) is designed to minimize both power consumption and chip area. The chip is designed and implemented in TSMC 0.18-μm CMOS technology. According to the experimental results, the output of this PLL oscillates at 402.9MHz and exhibits phase noise of -79 dBc/Hz at 100 kHz offset. The result shows that the cascade structure work well, while only consume 0.28mW in the first PLL and 0.46mW in the second PLL with a 1.8V supply voltage. The die area is 0.525 mm2. The proposed cascaded PLL has low power dissipation, small chip area, and no off-chip components or crystal oscillator. It is suitable for the integration with implantable medical system-on-chips (SOCs). Finally, a discussion about poor jitter performance when turning on two PLL in the same time is made and the improvement is proposed.