應用於高密度資料儲存之交錯電阻式記憶體之陣列層級分析

Abstract

電阻式記憶體(RRAM)被認為是其中一個可望取代傳統快閃記憶體(flash memories)的技術，目的為克服在元件微縮過程中快閃記憶體所遭遇的瓶頸。近幾年來，電阻式記憶體的製程趨向成熟，且具有優異特性的元件不斷推陳出新。無疑地，下個階段的發展勢必為實現可工作的高密度電阻式記憶體陣列實體。雖然有一些陣列雛型已被提出，但這些架構下的每一個電阻式記憶體單元，都必須搭配一個電晶體來分離不同的記憶體單元以隔絕單元之間的相互干擾。相較之下，交錯陣列的記憶體架構因為每一個記憶體單元具有最小二維面積4F2，在元件微縮的過程中更具潛力。然而，交錯電阻式記憶體陣列因為缺少電晶體的隔絕作用，其資料儲存容量受限於記憶體單元間的干擾。此論文藉由有系統的電路模擬及分析，評估各種過去被提出用來解決交錯陣列架構下記憶體間交互干擾方法之可行性，並且試圖歸納出未來發展的指南，以促進高資料儲存容量、高效能的交錯電阻式記憶體陣列的實現。 首先，我們將介紹在此分析中所使用的電阻式記憶體及其陣列的電路模型。不同特性的電阻式記憶體皆可被簡單的HSPICE電路模型所模擬出。簡化的交錯陣列亦或是考量線阻抗的實際交錯陣列也皆可利用此套電路模型來模擬，以幫助了後續探討的陣列層級分析。 我們接著利用解析以及數值方法，詳盡地探討不同的資料讀取方式。相較於僅將一條位元線(bit-line)的電壓拉升(pull-up)，拉升更多條位元線、甚至字元線(word-line)更能幫助達到更大的陣列密度。另外，利用拉升部分字元線的方式，可減低隨機讀取時的功率消耗。最後，線阻抗對於讀取以及寫入窗口(read and write margin)的影響也被探討。 除此之外，我們比較了目前最具前瞻性的三種型態的電阻式記憶體:CRS、1D1R、1S1R。這裡我們使用了平行讀取以及寫入的操作方式以探討此三類元件作為儲存類別記憶體(storage-class memories)的潛力。雖然這三種元件皆可實現高密度記憶體陣列的讀取操作，但CRS和1D1R在1-Mb陣列大小時的寫入遭遇瓶頸。1S1R因為同時兼具優異的平行讀取和寫入能力，被認為是最具發展潛力的下一世代儲存類別記憶體。 最後，我們也提出了針對1S1R電阻式記憶體的設計規範，此規範連結了元件特性以及電路效能。除了過去探討的讀取以及寫入干擾問題之外，此規範也採納了周邊電路的電流驅動能力為考量。此規範指出最大可行的陣列大小主要受限於寫入電流以及讀取窗口，而並非寫入干擾或是線阻抗。具有102~103的非線性電流電壓關係，且在低電壓區域電流值為1~10奈安培的元件，最有希望實現高密度1S1R交錯式陣列。

Resistive-switching random access memory (RRAM) has been regarded as one of the most promising candidates to overcome the scaling challenges faced by flash memory. In recent years, the development of RRAM has been getting more mature and various devices with superior characteristics have been widely reported. Therefore, the next critical step of RRAM development is to realize a functional high-density RRAM array. Although some prototypes of RRAM array have been successfully demonstrated, a selection transistor has to be integrated with each RRAM cell to avoid the interference among cells. By contrast, the high-density crossbar array with 4F2 cell size and no selection transistor is more desirable due to its superior scalability. However, the interference issue severely constraints the array size and thus the application for high-density data storage. In this thesis, we performed a systematic analysis on crossbar RRAM arrays to evaluate various approaches for mitigating the interference issue of future high-density data storage memory. The compact models of RRAM cells and crossbar arrays are used for array-level circuit analysis. Various device characteristics of RRAM can be effectively reproduced using a simple HSPICE model. Furthermore, the equivalent circuit models of crossbar arrays with and without interconnect line resistance are developed to assist array analyses. Comprehensive analytical and numerical circuit analyses on various read schemes are first discussed. In contrast to pulling up only one bit-line, pulling up all bit-liens and word-lines suppresses the interference and facilitates the implementation of a much larger crossbar array. Additionally, the partial bit-line pull-up scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed. Furthermore, some of the most interesting types of RRAM devices: complementary resistive switching (CRS), one diode-one resistor (1D1R), and one selector-one resistor (1S1R), are compared. Parallel read and write schemes are adopted to investigate their potential as storage-class memories. Although promising read performance can be realized in high-density CRS, 1D1R, and 1S1R crossbar arrays, unreliable write is the major obstacle in CRS and 1D1R arrays beyond the 1-Mb size. The 1S1R crossbar RRAM with excellent read and write margins using high-bandwidth parallel schemes has the most potential as a new-generation storage-class memory. Finally, the design rules connecting device characteristics and circuit performance are discussed to guide the future development of 1S1R RRAM, by taking into account of both read/write constrains and current driving capability of peripheral transistors. The maximum array size is mainly limited by write current and read margin rather than write disturb or interconnect resistance. A nonlinear IV with a current of 1~10 nA at the low voltage region and a nonlinearity factor of 102~103 is the most appropriate for implementing high-density 1S1R crossbar arrays.