具數位校正技術之低功率管線式類比數位轉換器設計

Abstract

隨著CMOS先進製程的演進，元件的尺寸變小以及元件整合度變高等特性，晶片可 以整合更多的電晶體元件，包含類比和數位兩個部份，使得單一系統晶片得以 實現。 其中，類比數位轉換器是用來將真實世界的連續訊號做轉換，量化成數 位訊號以方便之後的數位訊號處理器做處理。 管線式類比數位轉換器是目前被廣泛的使用在一個高速、中高解析度的應用上， 通常使用切換電容電路來實現，包含了運算放大器、類比開關和電容元件的使用 。 任何因為電容匹配度不夠或者是運算放大器的增益不足所造成的誤差，都會 降低類比數位轉換器的線性度，影響到輸出效能。

在先進製程技術下，因為元件本質增益下降以及低的操作電壓等因素，使得設計 一個高速、高增益的運算放大器變得相當的困難，也會產生很大的功率消耗。 而先進製程元件的參數除了本身變異度外，同時會受到元件擺放的位置以及周圍 電路的不同所產生的應力效應而有所變化。 這使得一些需要良好匹配才能正常工 作的電路，如電流鏡的設計，變得更為困難。 因為應力效應所導致的元件參數變化以及製程、電壓和溫度變化的影響，在電路 設計上必須要能涵蓋這些的變化範圍，因而產生了額外的功率消耗。 而使用數位 電路來提升類比電路的效能，在先進製程下，將被驗證為一個很有效率的方法。 如此，可以大幅的降低類比電路精確度的要求。

本論文的研究目標，主要發展一個強韌、高速、高效能且低功率消耗的類比數位 轉換器。 可以克服製程、電壓和溫度變化時的影響，並且可以隨著先進製程一同 做演進。 包含，發展了一個導通時間很短並且可以在高速下操作的切換放大器， 來降低功率消耗。 以及發展一個數位背景校正技術，在不影響轉換器正常的操 作下，來改善因為放大器增益不足和電容不匹配所造成的誤差。 並發展一個數位 偏壓的技術，利用校正所得到的數位資料，來觀察放大器輸出的安定情形，自動 的調整輸出偏壓電流的大小，滿足設計規格的要求，而不會產生過多的電流消耗 。 使用所發展的數位偏壓產生器來代替傳統的類比偏壓電路，產生電路所需要的 偏壓。 不須使用到任何的外部偏壓產生器和電流鏡，對於因為製程、溫度、電壓 、元件之間不匹配和元件老化所產生的變化，輸出偏壓都可以自動的調整到設計 規格所需要的大小。 因此，不需要像傳統的電路設計，為了提昇在量產時，不 同批晶片之間的良率，所需要保留夠大的設計邊際去涵蓋所有可能的變動範圍， 增加多餘的功率消耗。 此外，由於自動偏壓電路所產生的輸出電流，可以隨著操 作頻率成正比的變化，使得同一個轉換器可以在操作在不同的頻率應用下，都可 以有最小的功率消耗。

為了展示上述所提出的技術，我們設計了一個十位元、每秒三億次取樣的管線式 類比數位轉換器，並且使用65奈米的CMOS製程來製作。 操作在每秒三億次取樣 速率和1.0伏特的操作電壓下，整個類比數位轉換器的功率消耗為26.6毫瓦，內部 晶片面積為0.36平方毫米。 在輸入信號之頻率為一百萬赫茲時，可達到55.4dB 的信號對雜訊與失真比(SNDR)和67.2dB的無雜散信號動態範圍(SFDR)。 所發展的高速切換放大器電路，背景數位校正技術和數位偏壓技術，可以使 得轉換器在不同的製程、操作電壓和溫度變化下，輸出效能都能得以維持，並同 時保持較小的功率消耗。 此外，所發展的技術可以讓轉換器，能隨著先進製程 一同作演進的動作。

CMOS process scaling leads to lower supply voltages and small-size devices. With transistors becoming smaller and smaller, chips really become a system with both analog and digital portions inside. Analog-to-digital converters (ADCs) are used to convert real world analog signals into digital representations. The pipelined ADCs are widely used in high speed and medium-to-high resolution applications, due to their optimal tradeoff between conversion speed and resolution. Most of the pipelined ADCs are implemented by switched-capacitor (SC) circuits, comprise opamps, analog switches, and capacitors. The linearity of A/D conversion is mainly determined by high dc gain of opamp and matching of capacitors. Any errors caused by the finite dc gain of opamp or capacitors mismatch, will degrade the output performance of the ADCs.

In nanoscale CMOS technologies, the short-channel devices with the lower intrinsic gain and lower supply voltage make the design a high-speed and high-gain opamp becomes quite stringent, and produce a lot of power consumption. In addition to variances of the parameters, these parameters of nanoscale devices will be varied with device placement and the surrounding circuits. This makes some circuits that require a good match to work properly, such as the current mirror design becomes more stringent. As result of device parameters variations and process, supply voltage and temperature (PVT) variations, the circuit must be designed to cover the range of variations, resulting in additional power consumption. In nanoscale CMOS technologies, the performance of analog circuits can be improved by digitally assisted techniques, and will be verified as a very efficient way. So, it can greatly reduce the accuracy requirements of analog circuits.

The research objects of this thesis is mainly to develop a robust, high-speed, high performance and low power consumption of ADC. It can overcome the influence of the process, voltage and temperature variations, and can scale down with the evolution of nanoscale technologies. A high speed switching opamp is with very short turn-on time, is developed to reduce power consumption. The digital background calibration is developed to correct the A/D conversion errors caused by the low dc gain of opamps and capacitors mismatches. The digital bias technique monitors the settling behavior of opamp by the acquired calibration data and automatically adjusts bias currents in opamps, such that the settling behavior of opamps can be maintained without excessive current consumption. The digital bias circuits are used to replace the conventional bias circuits, produces the required bias voltages in analog circuits. Both external bias sources and current mirrors are not required, hence the matching requirements can be reduced significantly. The digital bias techniques are insensitive to fluctuations of PVT variations. Therefore, the design margins for each bias current of opamps can be further reduced on a chip by chip, reduction of power dissipation, chip area and a higher yield in mass production can be achieved. However, the digital bias techniques can track the operating frequency to produce appropriately bias voltage, thus the power consumption is proportional to operating frequency. As a result, the ADC which operates in different frequency applications as reconfigurable, is with minimal power consumption.

To demonstrate the above techniques, a 10-bit pipelined ADC was designed and fabricated using a 65 nm CMOS technology. Operating at 300~MS/s sampling rate, the ADC consumes 26.6~mW from a 1~V supply and occupies die area of 0.36~${\text{mm}}^2$. It achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.4 dB and a spurious-free dynamic range (SFDR) of 67.2 dB. According to the proposed techniques, the performance of the ADC could be maintained under various environmental changes.