標題: 具有補償頻率相依的I/Q不平衡效應機制以及單一指令多筆資料的算術邏輯運算單元之符合成本效益的頻域多輸入多輸出正交分頻多工收發機之設計與實作
Design and Implementation of Cost-Efficient SIMD ALU-based Frequency-Domain MIMO-OFDM Modem with Frequency Dependent I/Q Imbalance Compensator
作者: 賴煒棋
Lai, Wei-Chi
許騰尹
Hsu, Terng-Yin
資訊科學與工程研究所
關鍵字: 單一指令多筆資料;算術邏輯運算單元;時空區塊編碼;正交分頻多工;多輸入多輸出;頻率相依的I/Q不平衡效應;多相位和多速率時脈產生器;SIMD;ALU;STBC;OFDM;MIMO;FDI;MPRCG
公開日期: 2012
摘要: 本研究提出了一個以單一指令多筆資料(SIMD)的中央算術邏輯運算單元(ALU)為基礎的收發機架構,它可以用來改善基於時空區塊編碼(STBC)的4×4多輸入多輸出正交分頻多工(MIMO OFDM)系統下的硬體使用效率。在所提出的架構中,大多數的邏輯運算單元都被集中管理而可以被其他任何的演算法所共享;在這個中央ALU中,除了基本的加、減、乘、除之外,還另外提供了6個進階的指令集:複數乘法、複數除法、相關性運算、通道估計、基於4×4 STBC的反矩陣運算以及基於4×4 STBC的資料解碼。另外,為了可以順利控制此中央ALU下的各種資料路徑和訊號流程,一個排序器是非常必要的;而當有新的規格出現時,本篇所提出的架構相對於其他架構來說,較容易去重新配置以適應不同的規格。利用此提出的架構,一個基於前導訊號的低運算複雜度方法被開發出來對抗RF前端的I/Q增益、相位變化和濾波器不平衡效應(即被稱為頻率相依的I/Q不平衡效應(FDI));同時,一個全數位多相位和多速率時脈產生器(MPRCG)也被發展出來,它可以利用多相位的A/D時脈來將濾波器的偏移矯正,並支援快速的動態頻率調整來增加硬體使用效率,減少硬體的使用量。在VLSI實作方面,利用65nm 1P6M CMOS的製程,在1V的電壓輸入下,此晶片共需要1.87M gates以及33.7mW的功耗。
In this dissertation, a single instruction multiple data (SIMD) arithmetic logic unit (ALU)–based architecture is proposed to improve hardware efficiency in a 4×4 frequency-domain multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) modem based on a space-time block code (STBC). The majority of mathematic units in the proposed architecture are centralized so that any mathematic unit can be shared with any algorithm. Six advanced instructions are also defined in the ALU: complex multiplication, complex division, correlation, channel estimation, 4×4 matrix inversion, and STBC-based decoding. A scheduler is essential to handle all data paths and signaling flows smoothly with the use of a SIMD ALU. As a result, it is relatively easy to reconfigure the proposed design for different specifications. With this architecture, a low-computational-complexity preamble-assisted solution is developed to against variations in I/Q gains, phases, and filters of the RF frontend, namely frequency-dependent I/Q imbalance (FDI). An all-digital multiphase and multi-rate clock generator (MPRCG) was also built to tune I/Q timing coherently via multiphase A/D clocking and support fast dynamic frequency scaling for efficient implementation. The VLSI implementation of this chip, using an in-house 65-nm 1P6M CMOS process, consumes a total of 1.87 M gates and draws 33.7 mW at a supply voltage of 1 V.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079555856
http://hdl.handle.net/11536/72040
Appears in Collections:Thesis