高介電閘極層,間隙層構成,與矽鍺磊晶之製程研發以強化CMOS效能

Abstract

本篇論文提出半導體前段重要的三項製程技術之改善方案，包括高介電閘極結構製程，間隙層製程，以及矽鍺薄膜的沉積，前兩項製程技術可用來改善N型及P型金屬氧化層半導體的效益，第三項技術主要是可改善P型金屬氧化層半導體的效益。 在高介電閘極結構形成部分，在此提出一個結合高介電材料及金屬電極的整合性製程，以降低漏電流及電性氧化層厚度。此外，根據這個流程，可達到雙功函數金屬閘極的功能。 間隙層的製程改善部分，因為乙矽烷對溫度的低敏感度，在此提出用乙矽烷取代習用的矽烷來作為形成間隙層的原料，結果顯示可以改善薄膜沈積的均勻度達68% 及改善電流均勻度約9% ，並可同時提昇生產量及降低熱預算。 在沉積矽鍺薄膜的處理技術上，主要是在矽鍺薄膜沈積前，使用循環式的臭氧/氫氟酸清洗流程、低溫的氯化氫烘烤以及矽薄膜的沈積等前處理方法，用以沈積出低缺陷的矽鍺薄膜。實驗結果顯示，以此新製程所沉積的矽鍺薄膜可以提供約 2.4 倍的電洞遷移速率。也因為矽鍺薄膜提供了區域性壓應力而強化了電洞遷移速率，以及利用硼的摻雜技術來有效降低接觸電阻，所以可以進一步提升P型金屬氧化層半導體的電洞速率達32%。

In this work, gate stack formation for high-k materials, spacer process improvement and stress enhancement process before SiGe growth are proposed. The first two processes can improve the performance of pMOSFET and nMOSPET, and the third process can improve the pMOSFET performance. In gate stack formation, one feasible process flow integrating high-k and metal gate to decrease Jg (gate leakage) and EOT (electrical oxide thickness) without further impacting mobility is proposed, where dual work function metal gate can be formed by the proposed flow. For spacer process improvement, instead of using conventional silane-based nitride, disilane-based nitride is proposed to use on spacer here, since the disilane precursor is non-sensitive to temperature. The experimental results show the improvements on thickness uniformity by 68% and uniformity on Idsat variation by 9%. The throughput enhancement and thermal budget reduction are also achieved. In SiGe growth, an improved pre-treatment process is proposed by performing cyclical O3/DHF clean, low temperature HCl bake and Si seed growth prior to SiGe growth. Then the in-situ boron-doping SiGe is deposited with dislocation free. It is shown that hole mobility is enhanced around 2.4 times. Furthermore, combined effects from enhanced mobility provided by compressive local stress and in-situ boron doping to decrease contact resistance contribute the Ion gain enhancement around 32% for pMOSFET.