奈米壓印金屬網有機垂直電晶體

Abstract

近年來軟性電子元件與顯示器是新世代電子領域的研究重點，而擁有低成本、可大面積化與捲對捲量產製程優點的液態製程有機電晶體正具備此發展潛力。在過去的研究中，本實驗室已能製備出同時具有高輸出電流、高開關電流比與低操作偏壓等良好效能的液態製程有機垂直電晶體─空間電荷限制電晶體，其工作原理類似於真空三極管，以奈米網狀結構之基極控制垂直式通道的開關，進行電晶體的操作。然而，長久以來，我們的奈米網狀結構之基極受限於製程方式，人因時常影響我們分析不同製程條件下元件的電性。以往的研究顯示過大的電子傳輸通道會產生較大的漏電，導致開關比大幅降低，而過大的電子傳輸通道往往來自於製程中聚苯乙烯球所造成的聚集。 為了開發具有高穩定度與可大面積化的奈米網狀結構，奈米壓印是相當有潛力的 技術。本研究與台灣大學王倫教授實驗室合作，一同開發規則金屬網基極。為了進一步降低成本，使奈米壓印的商業價值獲得提升，研究中將原子層沉積法與奈米壓印結合，成功製備出規則金屬網，元件具有開電流 3.5 mA/cm2 以及開關電流比到 104 以上的元件特性。相信經過適當的製程改良後，更佳的元件特性將被期待。

In recent years, new-generation electronic field is focusing on flexible electronic devices and displays. Solution-processed organic transistor right has the potential for low-cost, large-area, and roll-to-roll process. In previous research, our lab has been able to fabricate solution-processed organic transistor with high output current, high on/off current ratio and low operation voltage named space-charge-limited transistor. Its working principle is similar to vacuum triode, switching vertical channel by nano-grid base electrode. However, our nano-grid base electrode is limited by the fabrication, and therefore human factors often affect our analysis of different process conditions. Previous research has demonstrated that large vertical electron-transport channels will cause large leakage current, resulting a lower on/off current ratio, and large vertical electron-transport channels are often resulting from the accumulation of polystyrene spheres in fabrication. In order to develop the nano-grid base electrode with high stability over a large area, nanoimprint lithography is a very promising technology. This work is cooperating with Prof. L. A. Wang’s lab, National Taiwan University, to develop base electrode with nano-grid array. In order to further reduce costs, further enhancing the commercial value, we combine the atomic layer deposition and nanoimprint lithography. We successfully fabricated vertical organic transistor with metallic nano-grid array. The on current is 3.5 mA/cm2 and the on/off current ratio is above 104. In the future, with further process optimization, a better device performance can be expected.