硬體導向之即時FastICA演算法 設計與實現

Abstract

本文提出了一種硬體導向之即時FastICA演算法的設計與實現，實現高維度預處理單元八通道腦電圖（EEG）信號分離。在硬體實現中，由於記憶體是有限的，即時FastICA的處理結果可能會產生不穩定。因此在本文中，我們提出與結合幾種方法，以提高即時FastICA的處理結果的穩定性。本文的主要貢獻如下。1）硬體導向之即時FastICA演算法設計具有較高的穩定性，2）平行運算單元硬體架構具有較少的運算時間。所提出的即時FastICA演算法使用台積電的90nm 1P9M CMOS製程實現。面積是1.469 x 1.469 mm2，八通道人造信號分離所需的功耗為65.0mW@100MHz為1V。

This thesis presents a stable hardware-oriented online FastICA algorithm that is implemented with high-dimensional preprocessing unit for eight-channel electroencephalogram (EEG) signal separation. Since the memory is limited in the hardware implementation, the online FastICA processing results may not be stable. Therefore, we propose several schemes in this thesis to improve the stability of the online FastICA processing results. The main contributions of this thesis are as follows. 1) Proposed hardware-oriented high-stable online FastICA algorithm, 2) Proposed low-computation-time hardware architecture with parallel one-units. The proposed online FastICA algorithm is implemented with TSMC 90nm 1P9M CMOS process. The core area is 1.469 x 1.469 mm2. The resulting power dissipation for eight-channel artificial signal separation is 65.0mW@100MHz at 1V.