以線性內插實現高密度液晶顯示驅動晶片設計

Abstract

本篇論文中，提出了一種新型具有數位類比轉換功能的輸出緩衝放大器，可以降低液晶顯示器之源極驅動器的成本與消耗功率。原理為緩衝放大器具有兩個輸入電壓準位，藉由控制輸入差動對的尾電流大小，改變兩輸入端的權重關係，使得緩衝放大器線性內插出一輸出電壓介於兩輸入電壓間。如此，藉由控制差動對的尾電流來產生數位類比轉換電路的功能，減少電阻串數位類比轉換器的階數，達到節省面積之功用。在文中，電路設計之概念與原理，以及實驗結果皆完整介紹與說明。本篇論文所提出的電路，使用TSMC 0.35m 2P4M製程模擬與實現，此晶片是具有十位元數位類比轉換器功能的輸出緩衝放大器，輸出緩衝器穩定時間為2.5sec，具有十位元數位類比轉換器功能的輸出緩衝放大器面積為0.0095mm2，僅需傳統八位元電阻串數位類比轉換器面積的38%。

A new output buffer amplifier with digital-to-analog converter (DAC) which reduces die area and power consumption has been proposed in this thesis for the source driver of small-size liquid crystal displays (LCDs). The purpose of this work is to control the tail currents of the input differential pairs. The interpolation amplifier divides the output voltage into two input voltage levels. By this way, a DAC function is created by controlling the tail currents of the input differential pairs. It reduces the bit depth of the resistor-string DAC (RDAC) and then saves the costs. The concepts, operational principles, and experiment results are introduced. The proposed circuit is simulated and fabricated via the TSMC 0.35m 2P4M process. This chip is a linear interpolation output buffer with a 10-bit DAC function. The settling time of the output buffer costs 2.5sec. The area of the proposed buffer amplifier with the 10-bit DAC is 0.0095mm2, which occupies only 38% of the conventional 8-bit RDAC and output buffer area.