具源極退化電感之CMOS共源極低雜訊放大器的設計及其分析

Abstract

本論文主要分析在低功耗低雜訊放大器之雜訊參數推導及其電路最佳化設計流程。通篇依序可以分成幾個部分： 第一部分主要在說明幾個，為了達成雜訊和阻抗匹配下的技術演進過程，及其各自所會面臨電路設計上的不足之處，並用一個折衷各方優點的技術，來做為本論文所討論的電路架構。 第二部分著重於，用雜訊參數來詳細分析不同技術的優缺點，由於同時雜訊和輸入阻抗匹配技術在尺寸上的不可設計性，導致必須外加一個電晶體尺寸的修正變數，來達成定電流或低功耗的設計，另一方面，由於人們常使用的家用頻段為5GHz以下，這讓用作匹配的閘極電感面積上升，進一步使得電感之內阻不可忽略，更會讓雜訊惡化，本論文會給出完整的雜訊指數式子。 第三部分使用TSMC 0.18-um CMOS製程，利用量測出來的數據，搭配短通道雜訊係數的近似值，將有的雜訊公式，配合設計流程，得出可以找出一個最佳的電晶體尺寸，在定電流下滿足雜訊匹配的結論，並透過這個尺寸，進一步找尋滿足雜訊匹配和阻抗匹配的電感和電容設計，以便做一個設計流程上的印證。 第四部分是全論文的總結。

The main idea of this thesis is to derive noise factor and to give optimal design flow of low power, cascode low-noise amplifier with on-chip inductor. This work consists of four parts: The first part mainly discusses some techniques for noise and impedance matching. But each technique has its own disadvantage, so we will make a comparison among them and finally use the most popular structure in this thesis. The second part analyzes the noise parameters of different techniques. The simultaneous noise and input matching structure can not be achieved for any transistor size, we need to add a parallel capacitor to eliminate this restriction for low power design. The complete formula of noise factor for simultaneous noise and input match are derived in this thesis. The third part, the theory derived is used to compare with the measured data of a CMOS LNA in TSMC 0.18 um CMOS process. A good agreement is demonstrated between the design theory and experimental results. The forth part, a conclusion is made in this thesis.