針對可重組態單電子電晶體陣列於構造限制下之面積最小化合成技術

Abstract

當製程演進至深次微米技術時，對於現今的電子電路與系統設計而言，功率損耗(power dissipation)已經成為一個重要的問題，特別是漏洩功率(leakage power)已經逐漸成為功率消耗的主要來源。近幾年，由於可重構單電子電晶體陣列(reconfigurable single-electron transistor array)的超低功率消耗，已經被視為有希望延伸摩爾定律的元件。目前已有很多針對可重構單電子電晶體陣列的自動化映射(automated mapping)方法被發展出來。然而，這些方法都只有在最後階段將構造限制(fabric constraints)納入考量，當他們被應用於實際實作時，這種方式得到的結果可能較無效率，如果我們在發展演算方法時早一步將這些限制納入考量，則單電子電晶體陣列映射的面積可以再變更小。本篇論文提出一個具限制感知(constraint-aware)的行排序(column ordering)方法以及動態的列排序(row ordering)方法來解決排序的問題。實驗結果顯示，與現行成效最好的方法比較，我們提出的方法可以改善六角形個數達到18%，並且在寬度上也能減少18%。

As fabrication process exploits even deeper submicron technology, power dissipation has become a crucial issue for electronic circuit and system design nowadays. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been considered as the promising device for continuing Moore’s Law due to its ultra-low power consumption. Several automated mapping approaches have been developed for the reconfigurable SET array. However, all of these approaches only consider fabrication constraints in last stages. When they are applied to real implementation the results could be inefficient. If we consider the constraints in earlier steps during developing algorithms, the area of SET array can be further minimized. In this thesis, we propose a constraint-aware column ordering and dynamic row ordering to tackle the ordering problems. Experimental results show that the proposed approaches can improve the number of hexagons and width up to 18% and 18% respectively as compared to an existing state-of-the-art approach.