閘極漏電流的變異對三維金氧半電晶體的影響

Abstract

當元件微縮到奈米世代以後，面臨了諸多的課題，諸如：短通道效應,元件特性的提升和閘極氧化層漏電流的問題都非常重要。幸運地，藉由各種不同的科技克服了種種的挑戰，舉例來說，使用極淺接面(ultra-thin junction)來克服短通道效應或strained Silicon來提昇元件性能等。然而，對於平面電晶體結構的discrete dopants造成的 變異性(variation)和漏電沒辦法克服。

所以在20奈米之後，考慮到良好的短通道效應的控制和可以減少random dopant fluctuation (RDF)的變異性，三面包覆閘極的電晶體元件變成了主流。但也由於3D 結構的問題，閘極氧化層的均勻性變成了限制，也產生在平面元件沒被注意到其他的問題－閘極漏電的變異。

本篇論文在研究探討在三面包覆閘極的電晶體元件上閘極漏電的變異的機制和主因，其中包括了製程上造成和stress之後造成的閘極漏電。在製程上造成的閘極漏電，閘極氧化層的表面平整度已經被認為是維持良好的閘極氧化層的品質和低閘極漏電的關鍵，然而，沒有量化方面的分析，可以直接的說明表面平整度和閘極漏電變異之前的關聯。

在本篇論文中，對於閘極漏電的變異提出了一個新的看法。首先，在三面包覆的電晶體元件的驗證上，發現閘極漏電的變異可以當作是閘極側壁表面平整度的指標，提出的理論和在不同Fin高度的三面包覆的電晶體元件的實驗可以驗證。結果顯示在越高的三面包覆的電晶體元件會增加表面不平整。其次，hot carrier 和NBTI stress也被實施在三面包覆的電晶體元件，我們發現NBTI stress會造成最嚴重的變異性。最後這個理論用在SRAM上去檢驗它的靜態功耗，結果確實顯示在pFET上，靜態功耗主要是受到NBTI的影響。

As devices are scaled to the nanoscale dimension, many problems such as short effect, performance enhancement, and leakage current are major challenges. Fortunately, many of them can be overcome by different technologies. For example, using ultrathin junction depth can solve the short channel effect, and strained silicon devices can enhance the electrical performance. However, the variation properties induced by the discrete dopants and leakage current are intolerant in the planar architecture.

Trigate device has then evolved as one of the candidates for devices beyond 20nm and have advantages such as good short channel control and variability, where random dopant fluctuation (RDF) can be suppressed. But, due to the 3D architecture, the uniformity of gate oxide becomes critical and raises another issue, gate current variation(Ig), which has not been a major concern that was not critical in planar devices before.

This thesis explores the mechanisms and the dominant factors of Ig in trigate devices which include the process-induced and the stress-induced gate leakage. While the surface roughness of gate dielectric layer has been reported to be the key for maintaining good oxide quality and lower gate leakage, no quantitative analysis has been done to justify the correlation between surface roughness and Ig.

This thesis proposes a new theory for determining surface roughness based on measuring gate current variation(Ig). By presenting and examining the results of experiments with trigate devices having various fin heights, this thesis offers the first quantitative analysis and experimentally verified linking of surface roughness to gate current variation. Additional confirmation is demonstrated through additional tests by performing hot carrier and NBTI stresses for trigate CMOS FETs. Finally, this theory was also validated through tests performed on the SRAM standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.