由實驗方法分析三維金氧半電晶體的彈道傳輸特性

Abstract

隨著元件微縮至100 nm 以下，短通道效應如DIBL跟Vth variation 皆更加嚴重，使元件的微縮更加困難。傳統抑制短通道效應的方法，諸如高濃度的基板參雜、極薄的閘極介電層等，在50 nm 以下皆不再能夠有效的抑制短通道效應。因此，採用新的材料和新的元件結構成為解決短通道效應最根本且有效的方法，如high –κ閘極介電層、metal Source/Drain、絕緣層上矽電晶體(Silicon on Insulator)和三閘極電晶體(Trigate)。其中，三閘極電晶體由於擁有和傳統VLSI CMOS相容的製程、極佳的電流傳輸特性跟抑制短通道的能力，被眾人寄望能延續莫爾定律到10 nm 以下。 由於元件縮小到奈米等級，探討電晶體的極限電流和載子傳輸機制的理論 ─ 彈道傳輸理論成為重要的議題。而在電晶體尚未完全到達彈道傳輸理論所說的無散射傳輸前，我們使用準彈道傳輸理論來分析載子在通道中傳輸的情形。在這篇論文中，我們首先介紹彈道傳輸理論的物理原理跟各個彈道參數，如入射速度 (Vinj) 跟彈道傳輸效率 (Bsat)。接著，我們介紹所使用的元件結構和製程技術，並展示我們所使用元件的基礎特性。實驗的結果顯示，三閘極電晶體對短通道效應有較強的抵抗力，在40 nm下仍不受短通道效應的影響。也因為全空乏(Fully-Depleted)的操作，三閘極電晶體擁有較佳的開關特性。在效能方面，三閘極電晶體也展露了較高的載子傳輸速度。之後，我們應用速度飽和模型(VSM)，以實驗的方法分析為何三閘極電晶體擁有較高的載子傳輸速度。分析的結果顯示，三閘極元件因為擁有較高的入射速度(Vinj)而有較佳的效能。而較高的入射速度則是源自三閘極電晶體的Double-Gate操作，使的載子受到較少的散射，而在汲極端有較高的載子遷移率，進而抬昇源極端的入射速度。最後，我們檢驗了在基極偏壓在三閘極元件中對傳輸特性的影響。結果顯示，儘管三閘極的寬度只有約50 nm，基極偏壓在調變Vth跟影響傳輸特性上仍然有效。 最後，我們得到了幾個顯著的結論: (1)我們成功的採用 VSM 的方法，用實驗擷取出彈道傳輸的參數。(2)在 40 nm 時，元件的整體效能主要是由入射速度所決定，而入射速度仍被汲極端的散射所限制住。(3)基極偏壓在調變三閘極電晶體的 Vth 跟影響傳輸特性上仍然有效;當施加順向基極偏壓時，反轉層電荷重心會被推離介電層的介面，因而擁有較高的遷移率。 本文中利用實驗淬取彈道傳輸參數方法，可以深入了解小尺寸元件載子傳輸的物理機制，對於未來在研究新的CMOS元件效能上的表現可提供重要的設計參考指標。

As channel length continues scaling down below 100 nm, the short channel effects, such as Vth variation and DIBL leakage, become increasingly important. To overcome these challenges, high-k gate dielectric layers, silicided source/drain, super halo doping, and 3D structures are the most possible solutions. Among all these new structures, the trigate MOSFET devices exhibit excellent I-V characteristics and manufacturing ability, which is believed to be able to continue Moore’s law down to 10 nm and beyond.

The ballistic theory has been extended to explore the transport efficiency in quasi-ballistic regime. In this thesis, we explicitly clarified quasi-ballistic transport theory and the physical meanings of each transport parameters, such as Bsat and vinj. Then, we outlined the advance devices used in this study and demonstrated the performance of tested devices. The results show that trigate CMOS devices are immune to short channel effects down to 40 nm and are superior to its planar ones. Furthermore, we applied Velocity Saturation Model (VSM) to trigate devices to examine the ballistic transport parameters experimentally. By using VSM to analyze ballistic transport property, we found that trigate devices show high injection velocity, which results from double gate operation that boosts the mobility of trigate device. On the other hand, planar device shows higher ballistic efficiency, which is attributed to stronger charge sharing ability of its drain. Finally, we examined the transport property of trigate devices under body bias conditions. It reveals that even when fin width is about 50nm, body bias is still effective in tuning the threshold voltage and transport property.

Several salient results are achieved: (1) we have successfully used VSM to extract ballistic transport parameters experimentally; (2) the injection velocity shows a more important role in the device overall performance, and it is limited by scatterings near the drain side; and (3) the body bias is effective in tuning Vth and affects transport property. When forward body bias is applied, the inversion charge centroid will be pushed away from the interface between oxide and channel, resulting in high mobility. These results will be helpful and valuable for the design of the next generation trigate CMOS devices beyond 20 nm.