标题: Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
作者: Chen, Shih-Hung
Ker, Ming-Dou
电机学院
College of Electrical and Computer Engineering
关键字: Electrostatic discharge;ESD protection design;ESD-transient detection circuit;power-rail ESD clamp circuit
公开日期: 1-五月-2009
摘要: The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal-oxide-semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection-circuit realized with smaller capacitance has been proposed and verified in a 0.13-mu m CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mistrigger and latch-on event under the fast-power-on condition.
URI: http://dx.doi.org/10.1109/TCSII.2009.2019164
http://hdl.handle.net/11536/7318
ISSN: 1549-7747
DOI: 10.1109/TCSII.2009.2019164
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 56
Issue: 5
起始页: 359
结束页: 363
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