24 GHz升頻器與降頻器

Abstract

本論文討論分為兩部分，其中所提到的電路之晶片製作皆由TSMC 0.18um mixed-signal/RF CMOS 1P6M製程實現。 第一部分為24 GHz降頻器，此電路是利用電容交錯耦合的差動轉導級來提升等效轉導且使用current bleeding使該開關切換更理想，此外，還使用了主動負載可以提供大的負載和穩定偏壓。此電路的量測結果為在22~26 GHz中功率增益大約是9 dB且雜訊指數大約是11.5 dB，P1dB為-15dBm，IIP3為-5 dBm，隔離度皆為-25 dB以下，功率損耗為4.9 mW且晶片面積為0.98x0.96 mm2。 第二部分為24 GHz升頻器，此電路轉導級使用多閘級電晶體的技術來改良線性度，且利用負阻抗補償來提升轉換增益。此電路的模擬結果為在功率增益大約是5.2 dB且雜訊指數大約是11 dB，OP1dB為-8.3dBm，IIP3為2.3 dBm，功率損耗為6.4 mW且晶片面積為0.88x1.05 mm2。

This paper consists of two parts. These proposed circuits are fabricated using a standard TSMC 0.18um CMOS process. Part I present a 24 GHz down-conversion mixer. The Capacitor cross-coupled differential transconductance stage is used to increase effective transconductance and decrease noise figure and the current bleeding is used to make the switching more ideal. We also use the active load to stabilize the bias of the mixer and it can provide a large load. The measurement result of the 24 GHz down-conversion mixer shows the power gain is about 9 dB in 22~26 GHz, noise figure is about 11.5 dB, P1dB is -15 dBm, IIP3 is -5 dBm, isolations are below -25 dB, power consumption is 4.9 mW and the chip size is 0.98x0.96 mm2. Part II proposes a 24 GHz up-conversion mixer. The multi-gate technology is used for transconductance stage to improve the linearity and we also use the negative resistance compensation to improve the conversion gain. The simulation of the mixer shows that the power gain is 5.2 dBm, noise figure is about 11 dB, OP1dB is -8.3 dBm, OIP3 is 2.3 dBm, isolation is under -20 dB, power consumption is 6.4 mW and the chip size is 0.88x1.05 mm2.