應用於無線基頻處理器之可適應等化器設計

Abstract

本論文研製之可適應等化器不但增強對抗一般多重路徑通道效應，更大大增強了對奇異性的多重路徑通道效應之抵抗力，而所提出之相位雜訊偵測與補償機制則大幅增加了對相位雜訊影響之容忍度。一般傳統的等化器一遇到所謂的奇異性多重路徑最大的問題就是在補償訊號的同時會增強雜訊，因此整個系統的效能往往被拖垮，因此我們提出了一個以導引信號為判斷依據然後於每段正交分頻多工符元更新一次的可適應等化器，在2.4 GHz的頻帶、IEEE衰減通道均方根延遲範圍50 ns的條件下，整體系統的效能比參考的演算法有高達6 dB左右的提升。 而考慮相位雜訊時這整個問題又不是如此單純了，系統效能隨著相位雜訊變大而嚴重衰減，因此我們發展出另一個結合相位雜訊與載波相位偏移的訊號模型，同時提出了一個相位雜訊偵測與結合載波相位偏移的補償架構。此演算法擴展了對相位雜訊的抵抗能力：從最大迴路頻寬7 ppm、最大迴路時間常數1.1 kHz至11 ppm、25 kHz。

A procedure against heavy multipath is developed in this thesis, which also can handle the ordinary multipath. Besides, another mechanism is proposed to extending the phase noise tolerance. The biggest problem of the conventional 1-tap equalizer is that it will enhance the noise while correcting the received signal once the singular channel occurs. Hence, we propose a pilot-based adaptive channel equalization that will update the channel information every OFDM symbol. In 2.4 GHz, the overall system performance gain is about 6 dB compared with the reference design for IEEE channel model with RMS delay spread 50 ns and 13 taps. Considering the phase noise, it is not so easy. Obviously, the system performance dramatically degrades when the phase noise increases. Therefore, we develop a new CFO joint phase noise model. The phase noise detection and compensation architectures are proposed at the same time. This algorithm extends the tolerance of phase noise from maximum loop bandwidth 7 ppm, maximum loop time constant 1.1 kHz to 11 ppm and 25 kHz in respectively.