標題: 應用於植入式神經輔具之互補式金屬氧化物半導體積體電路與系統晶片設計與分析
The Design and Analysis of CMOS Integrated Circuits and System-on-Chip (SoC) for Implantable Neural-Prosthetic Devices
作者: 陳煒明
Chen, Wei-Ming
吳重雨
Wu, Chung-Yu
電子工程學系 電子研究所
關鍵字: 生理訊號;前端放大器;植入式元件;神經輔具;Biopotential Signal;Analog Front-end Amplifier;Implantable Device;Neural prosthesis
公開日期: 2013
摘要: 近年來隨著醫療元件的快速發展,生理訊號擷取放大系統在健康監控、腦機介面以及神經輔具的應用上被大量的運用。其中精確擷取訊號的關鍵元件為前端訊號擷取放大器。而設計的挑戰在於生理訊號低振幅低訊號頻寬的特性。除此之外,為了進一步發展適用於臨床應用的醫療元件,各關鍵元件在設計中均盡量需降低系統功率消耗以及微小化系統面積。在本論文中將會探討植入式前端放大器以及神經輔具的系統架構以及設計技巧,並且利用所提出的設計概念實現三個晶片加以驗證。所實現出的系統除了功能驗證外,均經過動物實驗來驗證臨床應用的可行性。 第一個晶片實現了一個電壓模式八通道通用型互補式金屬氧化物半導體(CMOS)放大器電路。所提出的放大器電路利用0.18微米設計了八個斬波穩定放大器、一個八對一的類比多工器以及一個可程式增益放大器。利用虛擬電阻且不使用任何外部元件的設計下高通截止頻率可以低到0.8Hz且低通頻率可針對不同的生理訊號調整從1kHz到7kHz並提供74dB的增益。 第二顆晶片實現了一個電流模式的前端放大電路(CMFEA)。在此CMFEA中我們設計了一個前端電流放大器並結合了一個操作在非常低頻寬的主動迴授電路用以排除在電極-組織介面所產生的的偏移電流。此設計並不需要使用重置訊號或是高阻值的虛擬電阻。前端電流放大器中所設計的操作電流非常的低以壓抑功率消耗以及電流雜訊。一個可程式的電流增益級被設計來提供足夠的信號增益。一個電流模式低通濾波器被設計用來根據不同的生理訊號調整系統頻寬。根據此顆晶片的實驗結果,我們利用了新的迴授電路來消除直接偏移電流並實現一個非常低的高通點。 除了前端放大器外,第三個顆晶片實現了一個八通道閉迴路神經輔具系統晶片(SoC)用以對顱內腦波做即時的擷取放大、癲癇病症判斷以及適應性回授刺激治療。此SoC包含了八通道的前端放大器、一個十位元差值取樣類比數位轉換器、一個生理訊號處理器以及一個適應性高壓刺激器來針對顱內腦波做訊號擷取、癲癇訊號判斷以及回授抑制。除此之外此SoC還包含了一個無線系統,利用醫療頻段將編碼過的生理訊號做無線傳輸提供做為及時觀察以及利用線圈做感應式無線能量傳輸。利用動物實驗已驗證此SoC可以針對癲癇病癥做正確的判斷以及有效的迴授抑制。 經由晶片實現以及實驗驗證可總結出利用在本論文中所提出的系統架構以及設計方法所實現的電壓及電流模式放大器具有低功率消耗以及低雜訊的特性。這些特性可適用於生理訊號擷取放大並可提供醫療元件設計一個新的設計方向。除此之外,在論文中所實現的SoC展示了一個安全且有效的癲癇治療方式為下一世代臨床癲癇治療提供了一個具有潛力的臨床治療選擇。
In recent years, with the rapid development in technologies of medical devices, biopotential signal recording system is widely used in health monitoring, brain-machine interface, neural prosthesis, etc. The key element for medical devices is the analog front-end amplifier (AFEA) for accurate signal acquisition. The design challenge arises from the small-amplitude and low-frequency characteristics of the biopotential signal. Moreover, to further develop the medical device to clinical application, the device must be designed with the characteristics of low power consumption and small chip area. In this thesis, system architectures and key design techniques for implantable AFEA and neural-prosthetic device are discussed. To demonstrate the design concepts, three works are designed, implemented and tested. Except the functional verification, the designed devices are tested with Long-Evan rates to demonstrate the purpose of clinical application. In the first work, a voltage-mode 8-channel CMOS general-purpose AFEA circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFEA consists of eight chopper stabilized pre-amplifier, an 8-to-1 analog multiplexer, and a programmable gain amplifier. The AFEA is designed and fabricated in 0.18-μm CMOS technology. By adopting the pseudo resistor, the high-pass corner can achieve as low as 0.8Hz without external component and low-pass corner can be adjusted from 1 kHz to 7 kHz to suit for different kinds of biopotential signals with tunable gain up to 74 dB. In the second work, a current-mode front-end amplifier (CMFEA) for neural signal recording systems is implemented. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. Based on the experiment results, a low-power CMFEA is proposed and simulated. The deigned active feedback loop can bypass the DC offset current to realize a low high-pass cut-off frequency. In addition to the AFEA, an 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, epileptic seizure detection, and adaptive feedback stimulation control. The SoC is composed of 8 energy-efficient AFEAs, a 10b delta-modulated SAR ADC, a configurable bio-signal processor, and an adaptive high-voltage-tolerant stimulator. A wireless power-and-data transmission system is also embedded to transmit data and power wirelessly. The AFEA, ADC and BSP are used to record and recognize the seizures. Once a seizure is detected, the processor sends a command to activate the adaptive stimulator to suppress the aberrant brain activities. The recorded neural signals are transmitted to the outside of the body over MedRadio band (401 to 406MHz) for system monitoring. The power required for the SoC is transmitted through inductive coils over ISM band (13.56MHz). Data packets are encoded through cyclic redundancy check (CRC) for reliable data transmission. Verified on Long Evans rats, the proposed SoC can detect and feedback control the seizure correctly. From the implementation and measurement results, the proposed architecture and design methodology for voltage-mode and current-mode AFEAs show the low-noise and low-power characteristics which suit for biopotential signal recording and provide a promising solution for medical device. Moreover, the proposed SoC demonstrated an alternative, efficient, and safe treatment for closed-loop epileptic seizure treatment.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611831
http://hdl.handle.net/11536/73382
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