以積體電路架構實現應用在特徵影像套合之 隨機取樣一致性演算法

Abstract

隨著相機校正和影像處理的發展，近幾年影像套合在影像處理中已經佔有越來越重要的地位，其可應用的範圍也越來越廣泛。伴隨著以特徵搜尋的演算法出現，影像套合校正技術才慢慢趨近於成熟。 本篇論文主要是針對隨機取樣一致性演算法在特徵影像套合上的應用進行考量，進而提出適用於此演算法的電路架構，使其能與影像套合中前兩項步驟之硬體架構進行結合。而論文當中採用了交錯洗牌(interleaving)以及重新排列的方式來將儲存的匹配特徵點座標資料打散，以便達到隨機取樣的效果。參數求解的部分則是採用高斯消去法，其中包含以心臟收縮陣列(systolic array)架構實現向前消去法(forward elimination)，使其能保有資料僅在區域間溝通的優點。除此之外，本篇論文利用係數矩陣對稱的特性，大幅地減少心臟收縮陣列所需的處理單元數目。本篇論文也提出了應用查找表(lookup table)的除法電路架構，使得運算在一個週期內便可完成，而不需透過迭代(iteration)的方式。硬體方面的實現是透過硬體描述語言verilog，電路可以完成每秒30張影像輸入的及時處理，且影像的解析度是1024x1024，其時脈週期為100MHz。

With the camera calibration and image processing development in recent years, image registration has become more important in the image processing increasingly. The application of the image registration is also increasingly widespread. This thesis proposes a circuit implementation of RANdom SAmple Consensus (RANSAC)for feature-based image registration applications. In order to achieve the effect of random sampling, the interleaving and the group shuffling method are adopted to disorder the stored matching feature point coordinates. This thesis uses the systolic array architecture to implement the forward elimination step in the Gaussian elimination. The computational complexity in the forward elimination is reduced by sharing the coefficient matrix. As a result, the area of the hardware cost is reduced by more than 50%.The using of the look-up table for the divider circuit implementation make the calculation can be done in a single clock cycle without any iteration. The proposed architecture is realized by using verilog and achieves real-time calculation on 30fps 1024 * 1024 video stream on 100 MHz clock.