應用於多通道神經感測之可配置小波離散轉換

Abstract

在腦部功能研究中以及神經義肢實現上，具高整合及微小化之神經感測系統是近年來相當熱門的議題。本論文提出十六通道可配置式離散小波轉換應用在高密度神經感測系統當中，藉由轉換腦神經訊號(EEG/ECoG)到不同頻段這種方式，擷取腦神經訊號之特徵；所提出的可配置式離散小波轉換是採用提升式離散小波轉換演算法，此演算法可降低計算電路複雜度，進而有效地降低整體面積和功率的損耗。此外，在這個設計中時間窗格跟母小波都可以根據應用不同而調整。為了應用在能量有限的微小化神經感測系統上，本論文也採用了電源閘控技術及時脈閘控技術，利用此兩項技術可以更進一步降低整體的能量消耗。 藉由採用65奈米低功耗製程，本論文實現了四個四通道可配置離散小波轉換，可擷取十六通道腦神經訊號之特徵，只消耗了26微瓦功耗，面積為0.11平方毫米。此外，本論文更進一步將四個四通道可配置離散小波轉換實現在兩個MachXO2-1200ZE的現場可規劃邏輯陣列(FPGA)晶片上，並利用2.5D異質整合技術將這兩個現場可規劃邏輯陣列晶片整合至高密度神經感測微系統上，離散小波轉換整體功耗為211.2微瓦。

Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization for capturing accurate signals from an untethered subject in his natural habitat. In high-density neural sensing microsystems, a 16-channel configurable lifting-based DWT is proposed for extracting the features of EEG/ECoG signals by filtering the neural signal into different frequency bands. Based on the lifting-based DWT algorithm, the area and power consumption can be reduced by decreasing the computation circuits. Additionally, both the time window and mother wavelets can be adjusted. Moreover, the power-gating and clock-gating techniques are utilized to further reduce the energy consumption for the energy-limited bio-systems. The four proposed configurable 4-chanel DWTs are designed and implemented using TSMC 65nm CMOS Low power process with total area of 0.11 mm2 and power consumption of 26 µW. Moreover, this proposed DWT is also implemented in Lattice MachXO2-1200 FPGA and integrated in a high-density neural-sensing microsystem in 2.5D heterogeneous integration with power consumption of 211.2 µW.