藉由三維沃爾洛伊圖對於隨機晶格邊界在可堆疊NAND記憶體造成的變異特性之模擬與分析

Abstract

本論文藉由TCAD元件模擬探討隨機晶格邊界在可堆疊NAND記憶體造成的變 異特性。利用可以更精確地描述晶格邊界的沃爾洛伊圖像，我們分析了臨界電壓變異在元件通道長度(Lg)與高度(Hch)的微縮特性。 比較一維、二維以及三維晶格描述方法，我們發現當元件沿著通道高度(Hch)微縮時，三維沃爾洛伊圖可以反映較合理的變異性。因此，當我們考慮隨機晶格邊界引起的變異性時，三維的模擬方法是較被推薦的。除此之外，我們也利用三z沃爾洛伊圖探討隨機晶格邊界和隨機電報雜訊(RTN)的交互作用。根據我們的研究，三維晶格邊界會和帶電缺陷之間有不可忽視的交互作用。因此，在分析可堆疊NAND記憶體的RTN效應時，我們建議使用三維圖像模擬晶格邊界。

This thesis investigates the random grain-boundary-induced variabilities for stackable NAND flash with TCAD simulations. Using the Voronoi method to describe grain boundaries (GBs) more accurately, the VT variations with the scaling of channel length (Lg ) and channel height (Hch) are analyzed. Through the comparison between 1D, 2D and 3D grain methods, our study indicates that the 3D-Voronoi grain can show a more realistic variability when devices are downscaled along the channel height (Hch) direction. Therefore, a full 3D consideration is suggested when modeling the random GB induced variation. In addition, the interaction between the random GBs and single-interface-trap induced random telegraph noise (RTN) is also investigated using 3D-Voronoi patterns. Our study indicates that the grain boundaries described by 3D grains may strongly interact with the charged trap and should be considered when the RTN is analyzed in stackable NAND flash.