高介電係數材料/ 三五族金氧半電容器之研究

Abstract

三五族金氧半場效電晶體近年來已被廣泛的研究。比起傳統的矽材料，擁有較高的電子遷移率和較低的導通電壓，因此成為未來通道材料的首選，可望取代傳統以矽基板的互補式金氧半場效電晶體，應用於下一代低功耗、高速度的邏輯元件。然而，高介電係數材料以及高介電係數材料與三五族的界面問題阻礙了三五族元件的發展，如何提高電容值的同時亦能有良好的界面特性也成了一門研究課題，同時也是本論文的研究方向。而本論文中討論了三種不同基板與不同高界電係數材料的元件特性，可以分為三部分。 第一部分使用了成長於矽上，不同摻雜濃度的砷化銦鎵基板，探討退火溫度以及摻雜濃度對於介面的品質的影響，並與直接成長於磷化銦上的砷化銦鎵基板作比較。實驗結果顯示，在400 oC的高溫退火條件下，長於矽上的砷化銦鎵基板能有著與成長於磷化銦上的砷化銦鎵基板相近的界面性質。 第二部分是成長在砷化銦鎵上，由二氧化鉿和氧化鑭交互堆疊的結構作為氧化層的金氧半電容器，比較不同退火條件以及不同氧化層結構，對於界面品質以及材料的影響。實驗結果顯示，此種複合結構在500 oC的高溫退火後，能夠提供比純二氧化鉿更低的表面缺陷密度和較高的電容值，有著更佳的元件特性。 第三部分則是在不同的退火條件下，討論氧化鑭界面層對於二氧化鉿與銻化銦界面特性的影響。結果顯示，在350 oC的退火條件下，二氧化鉿能夠有著很低的等效電容厚度，並且加了氧化鑭界面層後，也能夠有效改善界面品質，大幅降低了表面缺陷密度。

III-V metal-oxide-semiconductor field effect transistors (MOSFETs) have been widely investigated in recent years. III-V materials have higher electron mobility and lower turn on voltages in comparison with conventional Si devices. Therefore, III-V materials are promising candidates to replace Si as the channel material for next generation low-power, high-speed complementary metal-oxide-semiconductor (CMOS) device for logic applications. However, the interfacial property between high-k and III-V materials is a big problem. This study focuses on the improvement of devices performance and interface property between high-k and III-V materials. The research topics can be divided into three parts. First, the n-In0.53Ga0.47As with different Si doping concentrations was grown for MOS capacitors. When the post deposition annealing (PDA) temperature is 400 oC, the n-In0.53Ga0.47As/Si MOS capacitors exhibited good interfacial properties close to those of n-In0.53Ga0.47As/InP MOS capacitors. Second, the high-k material for the composite structure of La2O3 and HfO2 was investigated for n-In0.53Ga0.47As MOS capacitors. The structures show better performance includes higher capacitance, lower interface traps densities (Dit) and lower capacitance equivalent thickness (CET) then those of HfO2. Third, the n-InSb for MOS capacitor was investigated. A good CET value was obtained for 6 nm HfO2 structure when PDA temperature was 350 oC. Furthermore, the device performances were further improved by inserting 1 nm La2O3 interfacial layer.