系統單晶片應用之靜電放電箝制電路與輸出緩衝器可靠度設計

Abstract

全晶片靜電放電防護設計架構中，靜電放電箝制電路(ESD Clamp Circuit)在靜電放電的轟擊下，能有效提供一靜電電流放電路徑，為影響整體靜電放電耐受度(ESD Robustness)的主要電路區塊。然而當進入奈米製程製作時，傳統的靜電放電箝制電路面臨到嚴重的閘極漏電流影響，進而使電路失去功能並產生更嚴重的能量損耗。為此，於論文第二章中，提出替代和改善方案，其中包括使用金屬-金屬間電容替代金氧半導體電容和利用電路技巧方法解決傳統靜電放電箝制電路的閘極漏電流問題。 另外，不同於奈米製程下所產生的問題，隨著系統單晶片應用的趨勢，高壓互補式金氧半製程已廣泛使用於系統單晶片製作，然而在高壓的操作環境下，元件低持有電壓(Holding Voltage)將造成類似閉鎖效應(Latchup-Like)的危險，尤其是將這些元件作為電源間靜電放電防護元件使用。因此於論文第三章中，為解決一實際案例於觸控面板(Touch Panel)控制電路的高操作電壓環境下，元件低持有電壓特性產生的類似閉鎖效應，提出一新型高壓靜電放電箝制電路。該新型設計可以提高持有電壓，並高於觸控面板控制電路的操作電壓。因此，新型設計可以避免產生類似閉鎖效應的危險。 當半導體元件相關參數持續微縮，內部核心電路元件的操作電壓亦會隨著持續下降以符合元件可靠度。然而在系統單晶片的電路區塊中，並非所有的電路應用皆隨著製程演進而降低操作電壓。因此在晶片系統中，還存在許多電路必須操作於一較高電壓環境中。在考量不同操作電壓環境對電路可靠度的影響，一般的輸入/輸出介面電路將不再適用。為了解決輸入/輸出介面於不同電壓操作下所產生的電路可靠度問題，系統單晶片應用中，必須要有混合電壓共容輸入/輸出緩衝器(Mixed-Voltage I/O Buffer)的使用。此外，另有相關具有可承受高電壓能力的邏輯電路被開發，使其能處理高電壓訊號。然而數位電路應用中，最基本的電路單元為互補式邏輯閘(Complementary Logic Gate)，如能在混合電壓共容輸出緩衝器應用上，注入互補式邏輯的原理，將能設計出具有混合電壓共容能力之新型態邏輯閘。因此於論文第四章中，延續先前的兩倍電壓共容輸出緩衝器的相關研究，提出新型兩倍電壓共容邏輯閘的設計，並只使用一倍電壓元件，其中包括兩倍電壓共容反閘(NOT Gate)、反及閘(NAND Gate)、反或閘(NOR Gate)。 此外，進入奈米製程後，元件尺寸和各項參數級距更細微的情況下，電路將會更容易受製程、電壓、溫度變異而影響。對於提供一驅動訊號的輸出緩衝器來說，電路輸出驅動訊號的迴轉率(Slew rate)極易受到製程、電壓、溫度變異而變動，如要使輸出驅動訊號能有較穩定的迴轉率，必須加入電路補償機制。因此，於論文第五章中提出一新型具製程、電壓、溫度變異補償之兩倍電壓共容輸出緩衝器。為了能偵測兩倍電壓操作環境的變異情況，補償電路必須具有可處理兩倍電壓訊號的能力，而前章節所提出的兩倍電壓共容邏輯閘，將能組成兩倍電壓共容製程、電壓、溫度變異補償電路。在兩倍電壓共容輸出緩衝器與兩倍電壓共容製程、電壓、溫度變異補償電路的結合下，兩倍電壓共容製程、電壓、溫度變異補償電路能提供補償碼，使輸出緩衝器在製程、電壓、溫度變異下，能有效調節輸出驅動能力，維持一較穩定之輸出迴轉率。

In the whole-chip ESD protection design scheme, the ESD clamp circuit could provide an effective ESD current discharging path under ESD stresses. With a good ESD protection arrangement in the IC, the ESD robustness is mainly decided by the ESD clamp circuit. However, the traditional design suffered the serious gate leakage issue in nanoscale CMOS processes. It results in malfunction and serious power consumption in the circuit. For solving the gate leakage issue in the traditional ESD clamp circuit, new proposed designs are presented in Chapter 2 which included usages of device replacement by metal-oxide-metal capacitor and circuit bias technique. In addition to the gate leakage issue in nanoscale CMOS processes, another reliability issue occurred in other CMOS technology node. With the development of SoC applications, the high-voltage CMOS technology is widely adapt in the ICs fabrication. But, under a higher operating voltage, the characteristic of low holding voltage in the device will cause the latchup-like failure, especially the devices were used as the ESD protection device in high-voltage CMOS processes. For solving the latchup-like issue in the high-voltage ESD clamp circuit, a new proposed design with latchup-free immunity is presented in Chapter 3. With the new proposed high-voltage ESD clamp circuit, the touch panel control IC is free to the latchup-like issue for the touch panel application. As MOS devices scaled down, the operating voltage of core devices were also reduced to lower voltage level (below 1.2 V). However, some peripheral components or sus-systems in the SoC application would be still operated in higher voltage levels (above 1.8 V). With different power supply voltages in the system, the conventional I/O buffers are no longer suitable due to reliability concerns. Therefore, the mixed-voltage I/O buffers are necessary to put into the interface to communicate with other sub-system which has different power domain. Moreover, some logic circuits were also developed with high-voltage tolerant ability to process higher voltage signal. In the digital circuit applications, the basic circuit units are complementary logic gates. If the mixed-voltage output buffer could infuse the logic operation theorem, the logic gates could be designed to have high-voltage tolerant ability. Base on design concepts of the 2xVDD-tolerant output buffer, new 2xVDD-tolerant logic gates with only 1xVDD devices are presented in Chapter 4, including 2xVDD-tolerant NOT, NAND, and NOR gates. When the CMOS process shrinks toward nanoscale, the circuit performance becomes more sensitive to process, voltage, and temperature (PVT) variations. Consequently, for providing the driving signal of an output buffer, the output slew rate will easily be varied by PVT variations. In order to keep a stable slew rate of the driving signal, the output buffer needs to combine the compensation mechanism. In Chapter 5, a new 2xVDD-tolerant output buffer with PVT compensation is proposed. For detecting the PVT variations under 2xVDD voltage environment, the compensation circuit needs to have the capability to process 2xVDD voltage signal. Simultaneously, the proposed 2xVDD-tolerant logic gates are able to constitute the 2xVDD-tolerant PVT compensation circuit. With the compensation code provided by the compensation circuit, the 2xVDD-tolerant output buffer can adjust the driving ability to keep a more stable output slew rate when facing PVT variations.