結合阻抗鎖定迴路之數位式低壓降線性穩壓器用以改善先進製程之低電源雜訊抑制能力

Abstract

隨著近年來半導體技術與消費市場的快速發展，單一功能的電子產品已無法滿足大部分消費者的期待。尤以可攜式裝置如智慧型手機、平板電腦等應用，因應更多功能整合於單晶片的趨勢，電源管理積體電路設計儼然成為不可或缺的一環。本研究專注於數位式低壓降線性穩壓器的開發工作，透過適當的電路設計技巧以達到低功耗、高電源雜訊抑制能力，以及可於低壓操作的電源管理模組。 傳統類比式操作的低壓降線性穩壓器多仰賴負迴授的機制穩定輸出電壓。為了使類比電路能夠正常操作，其輸入電壓通常需要較高的準位。舉常用的互補式金氧半導體製程為例，當輸入電壓低於一伏特時，多種堆疊結構的電路設計即不再適用，其原因為偏壓電路的設計將變得較為困難，使得這種類的電路設計需要更高深的設計技巧，對於非類比專業的設計師而言，將耗費更多的成本與開發時間。此外，隨著邏輯/混合訊號製程的演進，造成先進製程如深次微米，以至於奈米製程的世代，其元件開關的臨界電壓與元件額定操作電壓的比值逐漸上升，操作電壓也隨著開發過程逐漸下降等現象。這意味著當人們追求更高密度，更快速度的同時，也必須注意到這樣的發展趨勢對於電路設計所造成的衝擊。尤其是電源管理系統之設計，如何在這樣的發展趨勢下持續提供使用彈性，使得單一設計在未來開發的平台上持續適用，是吾們值得研究的課題。 本論文提出一結合阻抗鎖定迴路之數位式低壓降線性穩壓器，其目標為提供一高品質的電壓輸出供給後端電路使用。穩壓器核心採用數位雙向非同步波導管架構，可使電路操作於更低電壓並解決傳統數位控制器需要外部時脈訊號的麻煩，且於暫態響應事件結束後，最小化靜態電流的消耗。新加入的阻抗鎖定迴路，可協助輸出端抵抗來自切換式電壓轉換器的切換雜訊，提供更穩定電壓輸出。矽晶片樣本由聯電四零奈米製程實現，實驗結果證實此架構能達到約77%的雜訊抑制效果，最低操作電壓可達0.6伏特並正確提供0.4伏特的輸出準位。

In recent years, rapid growth of the semiconductor technology and electronic devices continuously enriches our daily life. Conventional single-function products gradually fade out from the market because those cannot satisfy the consumers’ expectations anymore. Especially for the portable devices such as smart phones and tablet PCs, power management integrated circuits (PMICs) become an essential block to deal with the various requirements from different circuits on silicon chips. This thesis focuses on digital low dropout regulator designs. Low-power, high power supply rejection (PSR), and capable of working under low-voltage environment power management module can be achieved through deliberated circuit designs. In general, most of analog low dropout regulators rely on the negative feedback mechanism to stabilize the output voltage. To make analog circuit working properly, the input voltage needs a relative high level. Taking the CMOS technologies as an example, when the input voltage falls below one volt, several stacking architectures like cascode stages are no longer useful. Biasing scheme becomes extremely difficult and therefore it increases the design effort. Besides, with the progress of the logic/mix-mode technologies, the ratio of transistor threshold voltage to nominal supply gradually increases. The supply voltage is also decreased to prevent the device from being damaged in deep sub-micron and nano-scale technologies. This trend forces us to consider the impact of the process evolution during the design jobs. This thesis proposes a resistance-locked loop embedded digital low dropout regulator to improve the PSR in advanced CMOS technologies. The bidirectional asynchronous wave pipeline architecture doesn’t need the external clock reference and thus the quiescent current can be minimized in steady-state. Moreover, the controller can work under a very lower input voltage. The ratio of the output voltage to input supply can be improved to avoid unnecessary loss. As for the resistance locked loop, it helps the output node free from noise generated by the switching regulator, providing a high quality output for the loading. The test chip was fabricated in UMC 40nm low-power CMOS process. Experimental results show a 77% noise suppression. The minimum supply voltage can be down to 0.6V and a 0.4 V regulated output can be guaranteed.