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dc.contributor.author陳昱宇en_US
dc.contributor.authorChen, Yu-Yuen_US
dc.contributor.author李義明en_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2014-12-12T02:38:26Z-
dc.date.available2014-12-12T02:38:26Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070060324en_US
dc.identifier.urihttp://hdl.handle.net/11536/73636-
dc.description.abstract近年來,在半導體產業中,因為電晶體尺寸不斷的微縮,元件的製程步驟更加繁複,為了維持摩爾定律(Moore’s Law)的運作,除了傳統的製程技術的突破外,更利用電晶體的結構創新,在眾多的結構中,鰭式場效應電晶體(FinFET),因為符合較低成本的需求,以及高效能的表現,成為這一個世代的重要的電子元件,同時金屬閘極暨高介電係數氧化層(HKMG)的技術,因能夠提升元件特性,而成為重要的技術,然而,在這些結構及技術之下,製程所造成的擾動對元件特性影響如何?是否得以壓抑等,都是有趣且值得去關切的學術研究議題,因此本研究將針對這個議題去作探討。 本研究探討了16奈米技術下金屬閘極暨高介電氧化層鰭式場效應電晶體的本質參數擾動,此擾動包含了隨機摻雜(RDF)、隨機介面陷阱(ITF)和隨機功函數(WKF)擾動,研究中利用了實驗數據校準過後的三維度的元件模擬進行。在此實驗中發現,對於不管是n型還是p型的電晶體,隨機摻雜和隨機功函數數擾動對整個特性變異占有較大的影響,而針對這個結果,我們進一步去分析對隨機摻雜下的隨機位置效應(Random Location Effect),我們發現在鰭式通道中的下半部,會有一個高能障的區域,是無法有效操作、利用的範圍,會導致較大的元件特性擾動。另一方面,本研究也去分析隨機功函數擾動在16奈米技術下鰭式場效應電晶體和平面式場效應電晶體(Planar MOSFET)下的反應,結果顯示隨機功函數擾動將被晶粒(grain)面積大小以及功函數的分佈所影響,且利用鰭式結構以及製作擁有較小面積的晶粒的閘極可以有效的抑制隨機功函數擾動。 總而言之,本研究所探討的結果,對台灣半導體產業相關技術,製程技術發展與元件設計有其正面的參考價值。zh_TW
dc.description.abstractInnovation of fabrication process, device, device material, and vertical channel structure benefits the mass production of CMOS devices. It continues to support and energize the performance projection of Moore’s law. Performance improvement of nanometerscaled CMOS devices requires not only overcoming a variety of fabrication challenges but also suppressing systematic variation and random effects. Except the process variation effects, the random effects including random dopants (RDs), interface traps (ITs), and work functions (WKs) are crucial for device characteristic of nanometer-scaled planar MOSFET and vertical channel field effect transistor, the bulk fin-typed field-effect-transistor. In this thesis, we estimate the influence of RDs, ITs, and WKs using the experimentally calibrated 3D device simulation on DC characteristic of high-k/ metal gate nand p-type bulk FinFETs. One of the main findings of this thesis shows the RDF and WKF are significant among fluctuation sources. Therefore, we further study the RDF and WKF for FinFET device. For RDF, the random position effect has been examined. We found that the bottom of the fin is the region which is with larger energy barrier in different aspect ratio (AR) FinFET. And this region will induce the larger fluctuation. On the other side, we explored the random-shaped generating technique to study the random WK-induced variability in the 16-nm FinFETs and planar MOSFET with amorphous-based TiN/HfO2 gate stacks. This reveals that the random WKF is affected by the random area and random location of the metal grain with different work function. The FinFET device and structure with a minimal metal grain size can effectively reduce characteristic fluctuation induced by the random nano-sized metal grains.en_US
dc.language.isoen_USen_US
dc.subject鰭式場效應電晶體zh_TW
dc.subject隨機離散摻雜zh_TW
dc.subject隨機金屬功函數擾動zh_TW
dc.subjectFinFETen_US
dc.subjectrandom dopant fluctuationen_US
dc.subjectrandom workfunction fluctuationen_US
dc.title離散摻雜位置效應以及隨機金屬晶粒在塊材鰭式場效應電晶體特性影響之研究zh_TW
dc.titleDC Characteristic Fluctuation of 16-nm-Gate HKMG Bulk FinFET Devices Induced by Random Position of Discrete Dopant and Random Grain of Metal Gateen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
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