完整後設資料紀錄
DC 欄位語言
dc.contributor.author黃柏翰en_US
dc.contributor.authorHaung, Po-Hanen_US
dc.contributor.author范倫達en_US
dc.contributor.author鍾崇斌en_US
dc.contributor.authorVan, Lan-Daen_US
dc.contributor.authorChung, Chung-Pingen_US
dc.date.accessioned2014-12-12T02:38:31Z-
dc.date.available2014-12-12T02:38:31Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070056126en_US
dc.identifier.urihttp://hdl.handle.net/11536/73663-
dc.description.abstract在本論文中,我們提出一個即時螢光訊號處理架構設計與實現。為了加速峰值檢測的速度以達到即時的時間限制,我們提出平行偵測硬體行為模型與改良峰值偵測程序,藉由拓展平行度,我們可以達到提高產能的目的,並且在改良峰值程序中縮短峰值偵測程序的處理時間。為了能夠精準地將細胞在適當時機分類,精準延遲秒數可經由延遲計數器的運算完成。目前在Zynq-7000 FPGA 開發模擬環境下,從給定的輸入測試資料模擬結果,FPGA從輸入資訊到輸出結果的時間約0.14毫秒。zh_TW
dc.description.abstractIn this thesis, we propose a real time fluorescence signal processing architecture for a microfluidic cell sorter. To speedup the peak detection with the constraint of the real time requirement, a parallel detection hardware behavior model and a modified peak detection procedure are proposed to increase the throughput by exploiting parallelism in peak detection and to reduce the partial latency of peak detection, respectively. In order to correctly actuate, the delay time to drive the piezoelectric actuator is precisely calculated by the delay counter. In the current implementation on Zynq-7000, the time from input test pattern to output through detection unit in FPGA is around 0.14ms.en_US
dc.language.isoen_USen_US
dc.subject細胞篩檢器zh_TW
dc.subject即時zh_TW
dc.subject實做zh_TW
dc.subjectcell sorteren_US
dc.subjectreal timeen_US
dc.subjectImplementationen_US
dc.title應用於微流體細胞篩檢系統之即時螢光訊號處理引擎設計與實現zh_TW
dc.titleDesign and Implementation of Real-time Fluorescence Signal Processing Engine for Microfluidic Cell Sorteren_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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