電阻式記憶體寫入速度及干擾困境之統計研究及快速預測方法

Abstract

電阻式記憶體 (RRAM) 有濳力成為新世代非揮發性記憶體的領先者，因其具有簡單的元件結構、低操作電壓及優秀的微縮能力。為了滿足非揮發性記憶體實際應用的規格要求，需要在寫入 (SET) 動作時有著高非線性的電壓對時間 (V-t) 關係以調整在高速寫入能力和干擾免疫性之間的取捨關係，這即為寫入速度及干擾困境。然而現今對寫入速度及干擾困境的研究中，大部分的研究都未考慮寫入時間 (tSET) 的隨機變動效應，即使寫入時間的變動分佈已知會涵蓋數個次方的時間範圍，這造成在預測寫入速度及干擾困境特性上相當大的誤差。因此建立一個考慮隨機變動效應的統計方法以預測寫入速度及干擾困境特性是非常需要的。 首先，我們提出一基於傳統氧化層崩潰理論的解析滲透模型 (percolation model) 來描述寫入時間的統計分佈行為，這個模型對於實驗數據中寫入時間變動的隨機行為和電壓時間關係提供了完整的解釋。再者本研究將在二個不同種類的電阻式記憶體上驗證此滲透模型的正確性，分別是基於氧缺細絲 (oxygen-vacancy filament) 切換機制的Ti/TiO2/Pt元件和基於金屬細絲 (metal filament RS) 切換機制的Ni/HfO2/Si元件。而時間電壓關係的冪次定律 (power-law) 行為也在涵括十次方的時間範圍內用定電壓應力法 (constant voltage stress) 進行驗證。 接著利用得出的韋伯分佈 (Weibull distribution) 和電壓加速關係，我們對寫入速度及干擾困境提出一個基於定電壓應力法測試的統計預測程序。然而使用一般的定電壓應力法做測試需要相當長的時間，因此我們證明由較秏時的定電壓應力法測試得到的韋伯分佈參數和電壓加速參數可以直接由斜坡電壓應力法萃取出來，接著再提出一個基於斜坡電壓應力法的快速預測方法來減少可靠度測試的時間。此外，我們也提出了元件設計守則以得到理想的寫入速度及干擾困境特性。最後利用在文獻中大量的斜式電壓應力測試數據，研究目前電阻式記憶體的現況可否達到寫入速度及干擾困境的嚴刻要求。 此論文對電阻式記憶體寫入速度及干擾困境在考慮寫入變動時間的統計行為下進行了一完整的分析，討論內容包括了理論架構、測試方法、元件設計守則及電阻式記憶體技術的現況。我們相信此研究對未來電阻式記憶體研究提供了一個相當有用的設計守則和測試方法理論。

Resistive-switching random access memory (RRAM) has the potential to become the front runner for future nonvolatile memory because of its simple structure, low operating voltage, and excellent scalability. To fulfill the requirement of nonvolatile memory application, the tradeoff between desired high SET speed and disturb immunity has to be carefully engineered using a highly nonlinear voltage-time (V-t) dependence at SET. This is also known as the SET speed-disturb dilemma. However, most studies have not considered the random variation effect of SET time (tSET) on the SET speed-disturb dilemma. The tSET variation is distributed across several orders of time, causing the unacceptable error in predicting the SET speed-disturb properties. Therefore, a statistical methodology for predicting the SET speed-disturb dilemma by considering the variation effect is needed. Firstly, we propose an analytical percolation model of tSET statistics, which is also based on the oxide breakdown theory. The model provides a thorough explanation of the stochastic nature of the tSET variation and voltage dependence of the experimental data. Furthermore, the validation of the percolation model was first performed on the SET variation of two distinct RRAM devices, Ti/TiO2/Pt based on oxygen-vacancy filament resistive switching (RS) and Ni/HfO2/Si based on metal filament RS. The power-law V-t dependence was also first verified across ten orders of magnitude in time using constant voltage stress (CVS). Then based on the Weibull distribution and voltage acceleration relation, we present a statistical projection procedure for SET speed-disturb properties using constant voltage stress (CVS). However, the conventional CVS testing requires substantial time. We demonstrated that the essential parameters of the Weibull distribution and voltage acceleration relation measured by time-consuming CVS testing can be extracted directly using a ramped voltage stress (RVS) testing, and then proposes a rapid prediction method based on RVS to reduce the time and cost of reliability testing. Furthermore, a device design guideline for the desired SET speed-disturb properties is discussed. Finally, because of the rich RVS data available in the literature, the current status of RRAM technology in meeting the strict requirement of the SET speed-disturb dilemma was discussed. This work performed comprehensive analyses of the SET speed-disturb dilemma of RRAM by considering statistical SET variation. The theoretical framework, testing methodology, device design guideline, and present status of RRAM technology are discussed. We believe that our research provides a useful design guideline and testing methodology for future RRAM researches.