新穎多晶矽奈米線非揮發性記憶體之研製與分析

Abstract

本論文研製高效能多晶矽奈米線場效電晶體與非揮發性記憶體元件，僅使用i-line的微影設備，完成多晶矽奈米線元件。另外，藉由“側壁邊襯源/汲極法”與“側向蝕刻法”，我們使用i-line的微影設備，成功地開發出通道長遠低於微影設備曝光極限的短通道多晶矽奈米線元件。 為瞭解多晶矽奈米線通道大小與形狀對矽-氧化矽-氮化矽-氧化矽-矽(SONOS)奈米線記憶體特性上的影響，藉由微調製程參數，我們製備出具有不同截面大小之方形與三角形奈米線環繞式記憶體元件。針對不同奈米線通道條件進行分析比較。在電性方面，由於採用環繞式奈米線，所有的奈米線多晶矽SONOS元件均展現出極陡的臨界擺幅與極小的漏極感應勢壘降低(DIBL)。在記憶體特性方面，由於三角形形狀奈米線尖端角度較大，尖角附近具有較強的電場，在穿隧層會有較大的能帶彎曲(band bending)，所以具有較高的寫入/抹除效率。 比較不同矽奈米線大小在對記憶體元件可靠度的影響，當奈米線的尺寸極小時，角落的強電場幾乎可覆蓋整條奈米線，整條矽奈米線通道上會有較均勻的電場，具有較好的寫入/抹除忍耐力。 為了開發高效能的奈米線多晶矽記憶體元件，本論文亦提出了一種克服傳統式NOR型快閃記憶體微縮瓶頸的三角形多晶矽奈米線浮閘記憶體，藉由採用具尖角的三角型奈米線通道，增強元件角落的電場，利用電子進入多晶矽浮閘會重新均勻分布的特性，使電子可持續的由尖端強電場處注入此浮閘奈米線記憶體且寫入窗口不會在短時間內飽和，因此，可在低電壓下操作同時具有極高的寫入/抹除效率。研究結果顯示在10伏特的寫入與負8伏特的抹除電壓下，不到0.1毫秒可有2.5伏特的寫入/抹除窗口。 除了利用結構的設計增進記憶體效能，論文亦提出能帶工程設計的方式來改進載子捕捉式記憶體效能的研究，第一種為將奈米矽晶粒埋入氮化矽中加強電荷的捕捉量研究，另一種則是以氧化鋁鉿為(HfAlO)電荷捕捉層的能帶工程研究，對前者而言，我們製作出多晶矽奈米線電晶體元件埋藏0、1、2層的奈米粒於氮化矽中，埋藏2層的奈米矽晶粒的元件雖呈現較慢的寫入/抹除速度，的確展現較大的記憶體窗口與較好的持久性。 此外，另一種設計之能帶工程氧化鋁鉿為電荷捕捉層的高效能非揮發性記憶體元件(簡稱氧化鋁鉿元件)，藉由微調氧化鋁鉿中的鋁/鉿比例，使在靠近穿隧氧化層端的氧化鋁鉿具有較小的能隙與較淺的捕捉層深度，增加電子被捕捉的機率。相反的，使在靠近阻擋層端，氧化鋁鉿層的能隙較大，捕捉層較深，所以電子不易克服阻擋層的氧化矽能障而散逸。總和上述原因，能帶-氧化鋁鉿元件具有與二氧化鉿元件相當的寫入/抹除效率。另外，由於有鋁元素掺於二氧化鉿為基底的薄膜中，使氧化鋁鉿會結晶溫度大幅提昇而抑制了退火後結晶現象的生成，因此能帶-氧化鋁鉿元件具有極佳的可靠度；高資料保持力與寫入抹除忍受力，歸因於非晶態的電荷捕捉層降低了晶界缺陷對可靠度造成的劣化。 在本論文中的最後提出一種低成本的短通道三閘極多晶矽奈米線場效電晶體製程，不需依賴昂貴的微影機台以自我對的方式用側壁形狀的提升式源/汲極縮短源/汲極距完成一百二十奈米通道長的電晶體、用側壁蝕刻法製作三閘極奈米線，完成二十五奈米的奈米線通道，電晶體元件顯示出極小的臨界擺幅與極低的汲極引發漏電流值。由於此製程下的元件通道長度與奈米線大小取決於製程條件的設計(如：乾蝕刻完成源/汲極邊襯時的蝕刻時間)，是具有高度彈性的製備方式，適用於一般實驗室以低成本製備不同材料的極小尺寸奈米線短通道元件。

In this dissertation, simple and low-cost self-aligned processes are proposed to fabricate high-performance polycrystalline silicon (poly-Si) nanowire (NW) field-effect transistors (FETs) and non-volatile memory (NVM) devices. Poly-Si NW devices with sub-lithographic channel length are successfully fabricated by “side-wall spacer technique” and “lateral etching technique” using only i-line based photolithography tool. Furthermore, both rectangular- and triangular-shaped NW devices are fabricated with fine-tuning process conditions. To investigate the influence of the channel size and shape of NW SONOS devices on memory characteristics, different channel sizes of rectangular- or triangular shaped gate-all-around (GAA) poly-Si NW SONOS memory devices are compared and analyzed. From the experimental results, it is observed that, owing to the enhancement of electric field around the sharp corners and larger band bending across the tunnel oxide, the triangular-shaped poly-Si NW devices show obviously higher programming/erasing (P/E) efficiency than that of the rectangular-shaped poly-Si NW devices. Also, as compared with NW devices with different channel size, the smaller NW channel devices show better endurance characteristics, and it is related to the more uniform stored electron distribution in the nitride CT-layer around the whole NW channel. On the development of high-performance poly-Si NVM devices, we have proposed a triangular-shaped poly-Si NW floating-gate (FG) memory device to overcome the conventional NOR-type memory scaling bottleneck. A GAA triangular-shaped NW channel configuration is intentionally adopted to increase the electric field of corner regions. Due to the electron redistribution properties of n+ poly-Si FG, extremely high and unsaturated P/E speed under low operation voltage is successfully demonstrated because the FG charge storage layer allows continuous electrons injection from the high electric field corner regions during programming. On the other hand, in order to further improve the performance of poly-Si NW charge trapping (CT)-type memory devices, two kinds of bandgap-engineered CT-layers are developed, one is silicon nanocrystals (Si-NCs) embedded in the nitride layer, and the other is bandgap-engineered HfAlO (BE-HfAlO) CT-layer. For the former CT-layer, we have fabricated poly-Si NW SONOS memory devices embedded with zero, single, and double Si-NCs layers in the CT nitride. NW memory devices with double Si-NCs layers exhibit slower P/E speed but larger memory window and longer retention time than those of conventional SONOS NW devices. For the second bandgap engineering work, we have designed a high performance device with BE-HfAlO CT layer. With gradually varying Al/Hf ratio in HfAlO film, the benefits of BE-HfAlO CT-layer come from the increased charge-trapping probability due to the smaller bandgap and shallower trapping level near the tunnel oxide, and the decreased charge loss probability due to the larger bandgap and deeper trapping level near the blocking oxide, therefore, the BE-HfAlO devices show high P/E speed, which is comparable to HfO2 CT-layer memory devices. Also, excellent retention and endurance characteristics are shown in BE-HfAlO devices due to the increase of the recrystallization temperature of Hf-based film incorporated with Al atom and elimination of the generation of grain boundaries in CT-layer. Finally, a high-performance short-channel tri-gated poly-Si NW FET is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Devices with channel length of 120 nm and NW thickness of 25 nm are successfully formed by the self-aligned process. The devices exhibit superior electrical characteristics due to the strong gate controllability, i.e., S.S. of 102 mV/dec, DIBL of 74.4 mV/V, and extremely high ION/IOFF ratio of 4.4 × 108. This flexible approach is feasible for fabricating test devices for probing the nano-scale phenomena and manufacturing of the future 3-D stackable devices/circuits.