低電壓高輸出擺幅類比前端電路應用EEG ECG記錄

Abstract

本論文提出一1V低電壓類比前端電路應用在生醫訊號測量。前端放大器會處理心電圖及腦波訊號並使用差動放大、截波穩定放大器與交流回授電路技術阻隔雜訊。本論文提出了一新的振幅延伸器可以在供應電壓受到限制的情況下加大輸出擺幅，並作為放大器及類比數位轉換器的介面。最後連續近似類比數位轉換器將生醫訊號轉換成數位訊號。前端放大器的功率消耗是1.83μW 。總功率消耗是6.92μW (不包含偏壓電路)。所提出的電路架構將被實現在TSMC CMOS 0.18 μm的製程，其晶片面積為1.51mm X 1.51mm (包含PAD)

This thesis presents a 1V low voltage analog front-end IC for biomedical signal acquisition. The front-end amplifier deals with Electrocardiogram (ECG) and Electroencephalogram (EEG) and rejects noise by differential and chopper-stabilized techniques with an AC feedback to reject low frequency noise. This thesis presents a novel amplitude extender which is an interface between the front-end amplifier and the successive approximation Analog-to Digital Converter (SAR ADC). Finally, A SAR ADC converts biomedical signal into digital signal. The power consumption of front-end amplifier is 1.83μW. The total power consumption is 6.92μW, biasing circuit excluded. The chip is realized in TSMC 1P6M 0.18μm CMOS process. The active die area is 1.51mm X 1.51mm.