利用有機化學氣相沉積法和非線性漸變緩衝層成長砷化銦鎵在砷化鎵基板上以及錯位應變和緩衝平台之研究

Abstract

本碩士論文主要研究以金屬有機化學氣相沉積系統(Metalorganic chemical vapor deposition) 磊晶成長高品質砷化銦鎵在砷化鎵基板上以及錯位應變和緩衝平台之研究。首先，將使用拋物線成長模式設計緩衝層並探討錯位應變(Misfit strain)對砷化銦鎵(In0.3Ga0.7As)表面形貌與磊晶品質之影響。本論文使用漸變緩衝層(Step grades buffer layer)技術成長砷化銦鎵(In0.3Ga0.7As)磊晶層於不同層數之漸變緩衝層，並於研究過程中觀察到當使用八層漸變緩衝層時，砷化銦鎵(In0.3Ga0.7As)表面形貌最為平坦(平均粗糙度:1.8nm);經由穿透式電子顯微鏡(TEM)結果顯示使用此磊晶條件所成長砷化銦鎵(In0.3Ga0.7As)層之缺陷密度(threading dislocation density)約為 4x106 cm-2 ;以上結果可知本研究已成功使用漸變緩衝層技術將砷化銦鎵(In0.3Ga0.7As)磊晶層成長於砷化鎵基板上。 本研究亦嘗試將砷化銦鎵化合物中銦含量提升至 50%，但磊晶層卻發生了相變化問題，因此嘗試使用提高成長溫度去抑制相變化的產生，並且由研究結果得知提高溫度確實能夠提高原子遷移距離並且成功的抑制相變化的發生。在解決相變化問題之後，本實驗嘗試探討減少緩衝平台厚度對表面形貌及晶格品質之影響，並於研究結果中得知當使用較薄的緩衝平台時(platform thickness 0.3 μm)，可以得到較好的表面形貌(平均粗糙度:2.4nm)，缺陷密度依舊可以維持在 2x106 cm-2 。本論文利用上述磊晶技術將高品質砷化銦鎵(In0.5Ga0.5As)磊晶層成長於矽基板上，並將其結構製作成高效能砷化鎵/砷化銦鎵(In0.5Ga0.5As)金氧半電容。並與本實驗室先前使用較厚緩衝平台(platform thickness 3 μm)所製作之金氧半電容作為比較，可以得到類似的電容-電壓(capacitance-voltage, C-V)與低頻率發散(frequency dispersion)等特性，並且所量測到其 Dit(interface trap density)值約為 3x1012 eV-1cm-2。

Future CMOS technology will aim at the integration of InGaAs semiconductor on silicon substrate for low-cost, light-weight, large area and high-performance logic devices. The first step toward the goal of InGaAs/Si is to obtain high-quality thin GaAs on Si substrate, then, InGaAs compound will be grown on the alternative GaAs/Si substrates. Therefore, this study concentrates on the growth of high-quality In0.5Ga0.5As epitaxial films on GaAs substrate for MOSCAP device application by using MOCVD growth method. For the purpose of study, the effects of misfit strain on crystal quality and surface morphology of In0.3Ga0.7As epilayers were first investigated. The epilayers were grown using parabolic method to design on different step graded buffer layers. AFM images show that smooth-surface In0.3Ga0.7As film with a RMS roughness of 1.8 nm was obtained at the 8-SG buffer layers. The threading dislocation (TD) density of about 4x106 cm-2 in the film was determined by TEM. High-quality smooth surface In0.5Ga0.5As epilayers have been successfully grown on the GaAs substrate. We have already reduced the platform thickness and total buffer layers reduce to 0.3 μm and 2.3 μm, respectively. A cross-section TEM image showed that the TDs have been successfully confined within the buffer layers designed to stop elongation of TDs into In0.5Ga0.5As epilayers, in our work a TD density of 2x106 cm-2 had been achieved. Finally, high-quality In0.5Ga0.5As epilayers allow us to fabricate high-performance In0.5Ga0.5As-based metal-oxide-semiconductor capacitor (MOSCAP) on GaAs substrate. The devices show a similar capacitance-voltage response, with small frequency dispersion. Acceptable interface trap density Dit value of 3x1012 eV-1cm-2 obtained by conductance methods was shown.